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Design_Details.md

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Block Diagram of the Entire Design

Block_Schematic

DAC Controller Design

Block Diagram of the DAC Controller

DA2_Component_block

Data stream needed for DAC Conversion

DA2_data

State Diagram of the DAC Controller

DA2_State Diagram

Filter Design

For Filter design we have taken help from MATLAB where we have used filter designer for finding the coefficients of the filter design.

Filter Specifications:

  • Sampling frequency: 50khz
  • Cut off frequency: 100 Hz
  • Stop frequency: 10KHz
  • Filter type: FIR lowpass Equiripple
  • Pass band magnitude gain: 0db
  • Stop band magnitude attenuation: 80db

Filter Designer Window of Matlab

Filter design specification analog model

Now from the quantization block in the filter designer the word lengths and fractional lengths are considered to find the coefficients.

  • Input word length: 12
  • Input fractional word length: 10
  • Output word length: 12
  • Output fractional word length: 10
  • Accumulator word length :12
  • Product word length: 24

Filter designer specifications for filter coefficient generation

Generated Coefficients

coefficients generated from the filter design

As these coefficients must be multiplied with the delayed input signal sequence as described in the data path they are converted in the fixed-point format as explained below: Say,

  • B = generated coefficient from the filter
  • C = B*2^10
  • D = nearest round figure of B
  • E = 12-bit binary format of D This E is the stored in as signed 12-bit in the constant called coefficient in VHDL program.

Block Diagram of the Filter

filter block diagram

Data-Path of the Designed Filter in VHDL

Filter_2

ADC Controller

The inbuilt ADC of the BASYS-3 board is instantiated and is utilized for the analog input of the signal to be filtered. This is available in the JXADC port of the BASYS-3 board. The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA's power rails, and a temperature sensor that is internal to the FPGA.