From 02afcf39e2f3b110345e104fa351fc2c505f1b4b Mon Sep 17 00:00:00 2001 From: Paul Keller Date: Wed, 22 Jan 2025 18:48:05 +0000 Subject: [PATCH] Optimize CB init for BH Early CB init not needed since BH does not copy to IRAM --- tt_metal/hw/firmware/src/brisc.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tt_metal/hw/firmware/src/brisc.cc b/tt_metal/hw/firmware/src/brisc.cc index 587acbd21d3..048cffe6106 100644 --- a/tt_metal/hw/firmware/src/brisc.cc +++ b/tt_metal/hw/firmware/src/brisc.cc @@ -40,7 +40,11 @@ constexpr uint32_t RISCV_IC_TRISC1_MASK = 0x4; constexpr uint32_t RISCV_IC_TRISC2_MASK = 0x8; constexpr uint32_t RISCV_IC_TRISC_ALL_MASK = RISCV_IC_TRISC0_MASK | RISCV_IC_TRISC1_MASK | RISCV_IC_TRISC2_MASK; +#ifdef NCRISC_HAS_IRAM constexpr uint32_t num_cbs_to_early_init = 4; // safe small number to overlap w/ ncrisc copy +#else +constexpr uint32_t num_cbs_to_early_init = 0; +#endif tt_l1_ptr mailboxes_t* const mailboxes = (tt_l1_ptr mailboxes_t*)(MEM_MAILBOX_BASE); uint32_t ncrisc_kernel_start_offset16; @@ -331,8 +335,10 @@ inline void finish_ncrisc_copy_and_run(dispatch_core_processor_masks enables) { l1_to_ncrisc_iram_copy_wait(); +#ifdef NCRISC_HAS_IRAM // Note: only ncrisc is in reset, so just deasserts ncrisc deassert_all_reset(); +#endif } }