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common.c
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common.c
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#define DEBUG_FLASH 0
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "stlink.h"
#include "stlink/mmap.h"
#include "stlink/logging.h"
#ifndef _WIN32
#define O_BINARY 0 //! @todo get rid of this OH MY (@xor-gate)
#endif
#ifdef _MSC_VER
#define __attribute__(x)
#endif
/* todo: stm32l15xxx flash memory, pm0062 manual */
/* stm32f FPEC flash controller interface, pm0063 manual */
// TODO - all of this needs to be abstracted out....
// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012)
#define FLASH_REGS_ADDR 0x40022000
#define FLASH_REGS_SIZE 0x28
#define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
#define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
#define FLASH_CR (FLASH_REGS_ADDR + 0x10)
#define FLASH_AR (FLASH_REGS_ADDR + 0x14)
#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
// STM32F10x_XL has two flash memory banks with separate registers to control the second bank.
#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44)
#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c)
#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50)
#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54)
#define FLASH_BANK2_START_ADDR 0x08080000
// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
#define FLASH_RDPTR_KEY 0x00a5
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xcdef89ab
#define FLASH_SR_BSY 0
#define FLASH_SR_EOP 5
#define FLASH_CR_PG 0
#define FLASH_CR_PER 1
#define FLASH_CR_MER 2
#define FLASH_CR_STRT 6
#define FLASH_CR_LOCK 7
//32L = 32F1 same CoreID as 32F4!
#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
#define FLASH_L1_FPRG 10
#define FLASH_L1_PROG 3
// G0 (RM0444 Table 1, sec 3.7)
#define STM32G0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
#define STM32G0_FLASH_ACR (STM32G0_FLASH_REGS_ADDR + 0x00)
#define STM32G0_FLASH_KEYR (STM32G0_FLASH_REGS_ADDR + 0x08)
#define STM32G0_FLASH_OPTKEYR (STM32G0_FLASH_REGS_ADDR + 0x0c)
#define STM32G0_FLASH_SR (STM32G0_FLASH_REGS_ADDR + 0x10)
#define STM32G0_FLASH_CR (STM32G0_FLASH_REGS_ADDR + 0x14)
#define STM32G0_FLASH_ECCR (STM32G0_FLASH_REGS_ADDR + 0x18)
#define STM32G0_FLASH_OPTR (STM32G0_FLASH_REGS_ADDR + 0x20)
#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24)
#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28)
#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C)
#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30)
#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34)
#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38)
#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80)
//32L4 register base is at FLASH_REGS_ADDR (0x40022000)
#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
#define STM32L4_FLASH_SR_BSY 16
#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */
#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
#define STM32L4_FLASH_CR_PG 0 /* Program */
#define STM32L4_FLASH_CR_PER 1 /* Page erase */
#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
#define STM32L4_FLASH_CR_STRT 16 /* Start command */
#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
// Bits requesting flash operations (useful when we want to clear them)
#define STM32L4_FLASH_CR_OPBITS \
((1lu<<STM32L4_FLASH_CR_PG) | (1lu<<STM32L4_FLASH_CR_PER) \
| (1lu<<STM32L4_FLASH_CR_MER1) | (1lu<<STM32L4_FLASH_CR_MER1))
// Page is fully specified by BKER and PNB
#define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB)
#define STM32L4_FLASH_OPTR_DUALBANK 21
//STM32L0x flash register base and offsets
//same as 32L1 above
// RM0090 - DM00031020.pdf
#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
#define FLASH_ACR_OFF ((uint32_t) 0x00)
#define FLASH_PECR_OFF ((uint32_t) 0x04)
#define FLASH_PDKEYR_OFF ((uint32_t) 0x08)
#define FLASH_PEKEYR_OFF ((uint32_t) 0x0c)
#define FLASH_PRGKEYR_OFF ((uint32_t) 0x10)
#define FLASH_OPTKEYR_OFF ((uint32_t) 0x14)
#define FLASH_SR_OFF ((uint32_t) 0x18)
#define FLASH_OBR_OFF ((uint32_t) 0x1c)
#define FLASH_WRPR_OFF ((uint32_t) 0x20)
//STM32F4
#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
#define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
#define FLASH_F4_CR_STRT 16
#define FLASH_F4_CR_LOCK 31
#define FLASH_F4_CR_SER 1
#define FLASH_F4_CR_SNB 3
#define FLASH_F4_CR_SNB_MASK 0xf8
#define FLASH_F4_SR_BSY 16
#define L1_WRITE_BLOCK_SIZE 0x80
#define L0_WRITE_BLOCK_SIZE 0x40
void write_uint32(unsigned char* buf, uint32_t ui) {
if (!is_bigendian()) { // le -> le (don't swap)
buf[0] = ((unsigned char*) &ui)[0];
buf[1] = ((unsigned char*) &ui)[1];
buf[2] = ((unsigned char*) &ui)[2];
buf[3] = ((unsigned char*) &ui)[3];
} else {
buf[0] = ((unsigned char*) &ui)[3];
buf[1] = ((unsigned char*) &ui)[2];
buf[2] = ((unsigned char*) &ui)[1];
buf[3] = ((unsigned char*) &ui)[0];
}
}
void write_uint16(unsigned char* buf, uint16_t ui) {
if (!is_bigendian()) { // le -> le (don't swap)
buf[0] = ((unsigned char*) &ui)[0];
buf[1] = ((unsigned char*) &ui)[1];
} else {
buf[0] = ((unsigned char*) &ui)[1];
buf[1] = ((unsigned char*) &ui)[0];
}
}
uint32_t read_uint32(const unsigned char *c, const int pt) {
uint32_t ui;
char *p = (char *) &ui;
if (!is_bigendian()) { // le -> le (don't swap)
p[0] = c[pt + 0];
p[1] = c[pt + 1];
p[2] = c[pt + 2];
p[3] = c[pt + 3];
} else {
p[0] = c[pt + 3];
p[1] = c[pt + 2];
p[2] = c[pt + 1];
p[3] = c[pt + 0];
}
return ui;
}
static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
uint32_t rdp;
stlink_read_debug32(sl, FLASH_WRPR, &rdp);
return rdp & 0xff;
}
static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t reg, res;
if (sl->flash_type == STLINK_FLASH_TYPE_F4)
reg = FLASH_F4_CR;
else if (sl->flash_type == STLINK_FLASH_TYPE_L4)
reg = STM32L4_FLASH_CR;
else
reg = FLASH_CR;
stlink_read_debug32(sl, reg, &res);
#if DEBUG_FLASH
fprintf(stdout, "CR:0x%x\n", res);
#endif
return res;
}
static inline uint32_t read_flash_cr2(stlink_t *sl) {
uint32_t res;
stlink_read_debug32(sl, FLASH_CR2, &res);
#if DEBUG_FLASH
fprintf(stdout, "CR2:0x%x\n", res);
#endif
return res;
}
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
uint32_t cr_lock_shift, cr = read_flash_cr(sl);
if (sl->flash_type == STLINK_FLASH_TYPE_F4)
cr_lock_shift = FLASH_F4_CR_LOCK;
else if (sl->flash_type == STLINK_FLASH_TYPE_L4)
cr_lock_shift = STM32L4_FLASH_CR_LOCK;
else
cr_lock_shift = FLASH_CR_LOCK;
return cr & (1 << cr_lock_shift);
}
static void unlock_flash(stlink_t *sl) {
uint32_t key_reg;
/* the unlock sequence consists of 2 write cycles where
2 key values are written to the FLASH_KEYR register.
an invalid sequence results in a definitive lock of
the FPEC block until next reset.
*/
if (sl->flash_type == STLINK_FLASH_TYPE_F4)
key_reg = FLASH_F4_KEYR;
else if (sl->flash_type == STLINK_FLASH_TYPE_L4)
key_reg = STM32L4_FLASH_KEYR;
else
key_reg = FLASH_KEYR;
stlink_write_debug32(sl, key_reg, FLASH_KEY1);
stlink_write_debug32(sl, key_reg, FLASH_KEY2);
if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) {
stlink_write_debug32(sl, FLASH_KEYR2, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_KEYR2, FLASH_KEY2);
}
}
static int unlock_flash_if(stlink_t *sl) {
/* unlock flash if already locked */
if (is_flash_locked(sl)) {
unlock_flash(sl);
if (is_flash_locked(sl)) {
WLOG("Failed to unlock flash!\n");
return -1;
}
}
DLOG("Successfully unlocked flash\n");
return 0;
}
static void lock_flash(stlink_t *sl) {
uint32_t cr_lock_shift, cr_reg, n;
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
cr_lock_shift = FLASH_F4_CR_LOCK;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
cr_lock_shift = STM32L4_FLASH_CR_LOCK;
} else {
cr_reg = FLASH_CR;
cr_lock_shift = FLASH_CR_LOCK;
}
n = read_flash_cr(sl) | (1 << cr_lock_shift);
stlink_write_debug32(sl, cr_reg, n);
if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) {
n = read_flash_cr2(sl) | (1 << cr_lock_shift);
stlink_write_debug32(sl, FLASH_CR2, n);
}
}
static void set_flash_cr_pg(stlink_t *sl) {
uint32_t cr_reg, x;
x = read_flash_cr(sl);
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
x |= 1 << FLASH_CR_PG;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
x &= ~STM32L4_FLASH_CR_OPBITS;
x |= 1 << STM32L4_FLASH_CR_PG;
} else {
cr_reg = FLASH_CR;
x = 1 << FLASH_CR_PG;
}
stlink_write_debug32(sl, cr_reg, x);
}
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
uint32_t cr_reg, n;
if (sl->flash_type == STLINK_FLASH_TYPE_F4)
cr_reg = FLASH_F4_CR;
else if (sl->flash_type == STLINK_FLASH_TYPE_L4)
cr_reg = STM32L4_FLASH_CR;
else
cr_reg = FLASH_CR;
n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
stlink_write_debug32(sl, cr_reg, n);
}
static void set_flash_cr_per(stlink_t *sl) {
const uint32_t n = 1 << FLASH_CR_PER;
stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr2_per(stlink_t *sl) {
const uint32_t n = 1 << FLASH_CR_PER;
stlink_write_debug32(sl, FLASH_CR2, n);
}
static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_mer(stlink_t *sl, bool v) {
uint32_t val, cr_reg, cr_mer, cr_pg;
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
cr_mer = 1 << FLASH_CR_MER;
cr_pg = 1 << FLASH_CR_PG;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
cr_pg = 1 << STM32L4_FLASH_CR_PG;
} else {
cr_reg = FLASH_CR;
cr_mer = 1 << FLASH_CR_MER;
cr_pg = 1 << FLASH_CR_PG;
}
stlink_read_debug32(sl, cr_reg, &val);
if (val & cr_pg) {
/* STM32F030 will drop MER bit if PG was set */
val &= ~cr_pg;
stlink_write_debug32(sl, cr_reg, val);
}
if(v)
val |= cr_mer;
else
val &= ~cr_mer;
stlink_write_debug32(sl, cr_reg, val);
}
static void set_flash_cr2_mer(stlink_t *sl, bool v) {
const uint32_t cr_pg = 1 << FLASH_CR_PER;
const uint32_t cr_mer = 1 << FLASH_CR_MER;
uint32_t val;
stlink_read_debug32(sl, FLASH_CR2, &val);
val &= ~cr_pg;
if (v)
val |= cr_mer;
else
val &= ~cr_mer;
stlink_write_debug32(sl, FLASH_CR2, val);
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
uint32_t val, cr_reg, cr_mer;
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
cr_mer = 1 << FLASH_CR_MER;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2);
} else {
cr_reg = FLASH_CR;
cr_mer = 1 << FLASH_CR_MER;
}
stlink_read_debug32(sl, cr_reg, &val);
val &= ~cr_mer;
stlink_write_debug32(sl, cr_reg, val);
}
static void set_flash_cr_strt(stlink_t *sl) {
uint32_t val, cr_reg, cr_strt;
if (sl->flash_type == STLINK_FLASH_TYPE_F4) {
cr_reg = FLASH_F4_CR;
cr_strt = 1 << FLASH_F4_CR_STRT;
} else if (sl->flash_type == STLINK_FLASH_TYPE_L4) {
cr_reg = STM32L4_FLASH_CR;
cr_strt = 1 << STM32L4_FLASH_CR_STRT;
} else {
cr_reg = FLASH_CR;
cr_strt = 1 << FLASH_CR_STRT;
}
stlink_read_debug32(sl, cr_reg, &val);
val |= cr_strt;
stlink_write_debug32(sl, cr_reg, val);
}
static void set_flash_cr2_strt(stlink_t *sl) {
uint32_t val;
stlink_read_debug32(sl, FLASH_CR2, &val);
val |= 1 << FLASH_CR_STRT;
stlink_write_debug32(sl, FLASH_CR2, val);
}
static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res, sr_reg;
if (sl->flash_type == STLINK_FLASH_TYPE_F4)
sr_reg = FLASH_F4_SR;
else if (sl->flash_type == STLINK_FLASH_TYPE_L4)
sr_reg = STM32L4_FLASH_SR;
else
sr_reg = FLASH_SR;
stlink_read_debug32(sl, sr_reg, &res);
return res;
}
static inline uint32_t read_flash_sr2(stlink_t *sl) {
uint32_t res;
stlink_read_debug32(sl, FLASH_SR2, &res);
return res;
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
uint32_t sr_busy_shift;
unsigned int res;
if (sl->flash_type == STLINK_FLASH_TYPE_F4)
sr_busy_shift = FLASH_F4_SR_BSY;
else if (sl->flash_type == STLINK_FLASH_TYPE_L4)
sr_busy_shift = STM32L4_FLASH_SR_BSY;
else
sr_busy_shift = FLASH_SR_BSY;
res = read_flash_sr(sl) & (1 << sr_busy_shift);
if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) {
res |= read_flash_sr2(sl) & (1 << sr_busy_shift);
}
return res;
}
static void wait_flash_busy(stlink_t *sl) {
/* todo: add some delays here */
while (is_flash_busy(sl))
;
}
static void wait_flash_busy_progress(stlink_t *sl) {
int i = 0;
fprintf(stdout, "Mass erasing");
fflush(stdout);
while (is_flash_busy(sl)) {
usleep(10000);
i++;
if (i % 100 == 0) {
fprintf(stdout, ".");
fflush(stdout);
}
}
fprintf(stdout, "\n");
}
static inline unsigned int is_flash_eop(stlink_t *sl) {
return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
}
static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
stlink_write_debug32(sl, FLASH_SR, n);
}
static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
/* todo: add some delays here */
while (is_flash_eop(sl) == 0)
;
}
static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
stlink_write_debug32(sl, FLASH_AR, n);
}
static inline void write_flash_ar2(stlink_t *sl, uint32_t n) {
stlink_write_debug32(sl, FLASH_AR2, n);
}
static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
uint32_t x = read_flash_cr(sl);
x &= ~(0x03 << 8);
x |= (n << 8);
#if DEBUG_FLASH
fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
#endif
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
uint32_t x = read_flash_cr(sl);
x &= ~FLASH_F4_CR_SNB_MASK;
x |= (n << FLASH_F4_CR_SNB);
x |= (1 << FLASH_F4_CR_SER);
#if DEBUG_FLASH
fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
#endif
stlink_write_debug32(sl, FLASH_F4_CR, x);
}
static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) {
stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1<<STM32L4_FLASH_SR_BSY));
uint32_t x = read_flash_cr(sl);
x &=~ STM32L4_FLASH_CR_OPBITS;
x &=~ STM32L4_FLASH_CR_PAGEMASK;
x &= ~(1<<STM32L4_FLASH_CR_MER1);
x &= ~(1<<STM32L4_FLASH_CR_MER2);
x |= (n << STM32L4_FLASH_CR_PNB);
x |= (1lu << STM32L4_FLASH_CR_PER);
#if DEBUG_FLASH
fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n);
#endif
stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
}
// Delegates to the backends...
void stlink_close(stlink_t *sl) {
DLOG("*** stlink_close ***\n");
if (!sl)
return;
sl->backend->close(sl);
free(sl);
}
int stlink_exit_debug_mode(stlink_t *sl) {
int ret;
DLOG("*** stlink_exit_debug_mode ***\n");
ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY);
if (ret == -1)
return ret;
return sl->backend->exit_debug_mode(sl);
}
int stlink_enter_swd_mode(stlink_t *sl) {
DLOG("*** stlink_enter_swd_mode ***\n");
return sl->backend->enter_swd_mode(sl);
}
// Force the core into the debug mode -> halted state.
int stlink_force_debug(stlink_t *sl) {
DLOG("*** stlink_force_debug_mode ***\n");
return sl->backend->force_debug(sl);
}
int stlink_exit_dfu_mode(stlink_t *sl) {
DLOG("*** stlink_exit_dfu_mode ***\n");
return sl->backend->exit_dfu_mode(sl);
}
int stlink_core_id(stlink_t *sl) {
int ret;
DLOG("*** stlink_core_id ***\n");
ret = sl->backend->core_id(sl);
if (ret == -1) {
ELOG("Failed to read core_id\n");
return ret;
}
if (sl->verbose > 2)
stlink_print_data(sl);
DLOG("core_id = 0x%08x\n", sl->core_id);
return ret;
}
int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) {
int ret;
ret = stlink_read_debug32(sl, 0xE0042000, chip_id);
if (ret == -1)
return ret;
if (*chip_id == 0)
ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address
return ret;
}
/**
* Cortex m3 tech ref manual, CPUID register description
* @param sl stlink context
* @param cpuid pointer to the result object
*/
int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
uint32_t raw;
if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw))
return -1;
cpuid->implementer_id = (raw >> 24) & 0x7f;
cpuid->variant = (raw >> 20) & 0xf;
cpuid->part = (raw >> 4) & 0xfff;
cpuid->revision = raw & 0xf;
return 0;
}
/**
* reads and decodes the flash parameters, as dynamically as possible
* @param sl
* @return 0 for success, or -1 for unsupported core type.
*/
int stlink_load_device_params(stlink_t *sl) {
ILOG("Loading device parameters....\n");
const struct stlink_chipid_params *params = NULL;
stlink_core_id(sl);
uint32_t chip_id;
uint32_t flash_size;
stlink_chip_id(sl, &chip_id);
sl->chip_id = chip_id & 0xfff;
/* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
if (sl->chip_id == 0x411) {
uint32_t cpuid;
stlink_read_debug32(sl, 0xE000ED00, &cpuid);
if ((cpuid & 0xfff0) == 0xc240)
sl->chip_id = 0x413;
}
params = stlink_chipid_get_params(sl->chip_id);
if (params == NULL) {
WLOG("unknown chip id! %#x\n", chip_id);
return -1;
}
if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) {
WLOG("Invalid flash type, please check device declaration\n");
sl->flash_size = 0;
return 0;
}
// These are fixed...
sl->flash_base = STM32_FLASH_BASE;
sl->sram_base = STM32_SRAM_BASE;
stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size);
if (params->flash_size_reg & 2)
flash_size = flash_size >>16;
flash_size = flash_size & 0xffff;
if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
sl->flash_size = 128 * 1024;
} else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) {
sl->flash_size = (flash_size & 0xff) * 1024;
} else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) {
// 0 is 384k and 1 is 256k
if ( flash_size == 0 ) {
sl->flash_size = 384 * 1024;
} else {
sl->flash_size = 256 * 1024;
}
} else {
sl->flash_size = flash_size * 1024;
}
sl->flash_type = params->flash_type;
sl->flash_pgsz = params->flash_pagesize;
sl->sram_size = params->sram_size;
sl->sys_base = params->bootrom_base;
sl->sys_size = params->bootrom_size;
//medium and low devices have the same chipid. ram size depends on flash size.
//STM32F100xx datasheet Doc ID 16455 Table 2
if(sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
sl->sram_size = 0x1000;
}
ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
// TODO make note of variable page size here.....
ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n",
sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
(unsigned int)sl->flash_pgsz);
return 0;
}
int stlink_reset(stlink_t *sl) {
DLOG("*** stlink_reset ***\n");
return sl->backend->reset(sl);
}
int stlink_jtag_reset(stlink_t *sl, int value) {
DLOG("*** stlink_jtag_reset ***\n");
return sl->backend->jtag_reset(sl, value);
}
int stlink_run(stlink_t *sl) {
DLOG("*** stlink_run ***\n");
return sl->backend->run(sl);
}
int stlink_set_swdclk(stlink_t *sl, uint16_t divisor) {
DLOG("*** set_swdclk ***\n");
return sl->backend->set_swdclk(sl, divisor);
}
int stlink_status(stlink_t *sl) {
int ret;
DLOG("*** stlink_status ***\n");
ret = sl->backend->status(sl);
stlink_core_stat(sl);
return ret;
}
/**
* Decode the version bits, originally from -sg, verified with usb
* @param sl stlink context, assumed to contain valid data in the buffer
* @param slv output parsed version object
*/
void _parse_version(stlink_t *sl, stlink_version_t *slv) {
uint32_t b0 = sl->q_buf[0]; //lsb
uint32_t b1 = sl->q_buf[1];
uint32_t b2 = sl->q_buf[2];
uint32_t b3 = sl->q_buf[3];
uint32_t b4 = sl->q_buf[4];
uint32_t b5 = sl->q_buf[5]; //msb
// b0 b1 || b2 b3 | b4 b5
// 4b | 6b | 6b || 2B | 2B
// stlink_v | jtag_v | swim_v || st_vid | stlink_pid
slv->stlink_v = (b0 & 0xf0) >> 4;
slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
slv->swim_v = b1 & 0x3f;
slv->st_vid = (b3 << 8) | b2;
slv->stlink_pid = (b5 << 8) | b4;
return;
}
int stlink_version(stlink_t *sl) {
DLOG("*** looking up stlink version\n");
if (sl->backend->version(sl))
return -1;
_parse_version(sl, &sl->version);
DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, STLINK_USB_VID_ST);
DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
DLOG("swim version = 0x%x\n", sl->version.swim_v);
if (sl->version.jtag_v == 0) {
DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
}
if (sl->version.swim_v == 0) {
DLOG(" notice: the firmware doesn't support a swim interface\n");
}
return 0;
}
int stlink_target_voltage(stlink_t *sl) {
int voltage = -1;
DLOG("*** reading target voltage\n");
if (sl->backend->target_voltage != NULL) {
voltage = sl->backend->target_voltage(sl);
if (voltage != -1) {
DLOG("target voltage = %ldmV\n", voltage);
} else {
DLOG("error reading target voltage\n");
}
} else {
DLOG("reading voltage not supported by backend\n");
}
return voltage;
}
int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) {
int ret;
ret = sl->backend->read_debug32(sl, addr, data);
if (!ret)
DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr);
return ret;
}
int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
return sl->backend->write_debug32(sl, addr, data);
}
int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
if (len % 4 != 0) {
fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
abort();
}
return sl->backend->write_mem32(sl, addr, len);
}
int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_read_mem32 ***\n");
if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
len % 4);
abort();
}
return sl->backend->read_mem32(sl, addr, len);
}
int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
DLOG("*** stlink_write_mem8 ***\n");
if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
len);
abort();
}
return sl->backend->write_mem8(sl, addr, len);
}
int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) {
DLOG("*** stlink_read_all_regs ***\n");
return sl->backend->read_all_regs(sl, regp);
}
int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) {
DLOG("*** stlink_read_all_unsupported_regs ***\n");
return sl->backend->read_all_unsupported_regs(sl, regp);
}
int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
DLOG("*** stlink_write_reg\n");
return sl->backend->write_reg(sl, reg, idx);
}
int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) {
DLOG("*** stlink_read_reg\n");
DLOG(" (%d) ***\n", r_idx);
if (r_idx > 20 || r_idx < 0) {
fprintf(stderr, "Error: register index must be in [0..20]\n");
return -1;
}
return sl->backend->read_reg(sl, r_idx, regp);
}
int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) {
int r_convert;
DLOG("*** stlink_read_unsupported_reg\n");
DLOG(" (%d) ***\n", r_idx);
/* Convert to values used by STLINK_REG_DCRSR */
if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
r_convert = 0x14;
} else if (r_idx == 0x40) { /* FPSCR */
r_convert = 0x21;
} else if (r_idx >= 0x20 && r_idx < 0x40) {
r_convert = 0x40 + (r_idx - 0x20);
} else {
fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
return -1;
}
return sl->backend->read_unsupported_reg(sl, r_convert, regp);
}
int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) {
int r_convert;
DLOG("*** stlink_write_unsupported_reg\n");
DLOG(" (%d) ***\n", r_idx);
/* Convert to values used by STLINK_REG_DCRSR */
if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */
r_convert = r_idx; /* The backend function handles this */
} else if (r_idx == 0x40) { /* FPSCR */
r_convert = 0x21;
} else if (r_idx >= 0x20 && r_idx < 0x40) {
r_convert = 0x40 + (r_idx - 0x20);
} else {
fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n");
return -1;
}
return sl->backend->write_unsupported_reg(sl, val, r_convert, regp);
}
bool stlink_is_core_halted(stlink_t *sl)
{
bool ret = false;
stlink_status(sl);
if (sl->q_buf[0] == STLINK_CORE_HALTED)
ret = true;
return ret;
}
int stlink_step(stlink_t *sl) {
DLOG("*** stlink_step ***\n");
return sl->backend->step(sl);
}
int stlink_current_mode(stlink_t *sl) {
int mode = sl->backend->current_mode(sl);
switch (mode) {
case STLINK_DEV_DFU_MODE:
DLOG("stlink current mode: dfu\n");
return mode;
case STLINK_DEV_DEBUG_MODE:
DLOG("stlink current mode: debug (jtag or swd)\n");
return mode;
case STLINK_DEV_MASS_MODE:
DLOG("stlink current mode: mass\n");
return mode;
}
DLOG("stlink mode: unknown!\n");
return STLINK_DEV_UNKNOWN_MODE;
}
// End of delegates.... Common code below here...
// Endianness
// http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
// const int i = 1;
// #define is_bigendian() ( (*(char*)&i) == 0 )
unsigned int is_bigendian(void) {
static volatile const unsigned int i = 1;
return *(volatile const char*) &i == 0;
}
uint16_t read_uint16(const unsigned char *c, const int pt) {
uint32_t ui;
char *p = (char *) &ui;
if (!is_bigendian()) { // le -> le (don't swap)
p[0] = c[pt + 0];
p[1] = c[pt + 1];
} else {
p[0] = c[pt + 1];
p[1] = c[pt + 0];
}
return ui;
}
// same as above with entrypoint.
void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
stlink_write_reg(sl, addr, 15); /* pc register */
stlink_run(sl);
while (stlink_is_core_halted(sl))
usleep(3000000);