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ArchitecturalMsr.h
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ArchitecturalMsr.h
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/** @file
Intel Architectural MSR Definitions.
Provides defines for Machine Specific Registers(MSR) indexes. Data structures
are provided for MSRs that contain one or more bit fields. If the MSR value
returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
May 2018, Volume 4: Model-Specific-Registers (MSR)
**/
#ifndef __INTEL_ARCHITECTURAL_MSR_H__
#define __INTEL_ARCHITECTURAL_MSR_H__
/**
See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
@endcode
@note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
**/
#define MSR_IA32_P5_MC_ADDR 0x00000000
/**
See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
@endcode
@note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
**/
#define MSR_IA32_P5_MC_TYPE 0x00000001
/**
See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
at Display Family / Display Model 0F_03H.
@param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
@endcode
@note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
**/
#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
/**
See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
Display Model 05_01H.
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
@endcode
@note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
**/
#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
/**
Platform ID (RO) The operating system can use this MSR to determine "slot"
information for the processor and the proper microcode update to load.
Introduced at Display Family / Display Model 06_01H.
@param ECX MSR_IA32_PLATFORM_ID (0x00000017)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_PLATFORM_ID_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
@endcode
@note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
**/
#define MSR_IA32_PLATFORM_ID 0x00000017
/**
MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1 : 32;
UINT32 Reserved2 : 18;
///
/// [Bits 52:50] Platform Id (RO) Contains information concerning the
/// intended platform for the processor.
/// 52 51 50
/// -- -- --
/// 0 0 0 Processor Flag 0.
/// 0 0 1 Processor Flag 1
/// 0 1 0 Processor Flag 2
/// 0 1 1 Processor Flag 3
/// 1 0 0 Processor Flag 4
/// 1 0 1 Processor Flag 5
/// 1 1 0 Processor Flag 6
/// 1 1 1 Processor Flag 7
///
UINT32 PlatformId : 3;
UINT32 Reserved3 : 11;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_PLATFORM_ID_REGISTER;
/**
06_01H.
@param ECX MSR_IA32_APIC_BASE (0x0000001B)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_APIC_BASE_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_APIC_BASE_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_APIC_BASE_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
@endcode
@note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
**/
#define MSR_IA32_APIC_BASE 0x0000001B
/**
MSR information returned for MSR index #MSR_IA32_APIC_BASE
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved1 : 8;
///
/// [Bit 8] BSP flag (R/W).
///
UINT32 BSP : 1;
UINT32 Reserved2 : 1;
///
/// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
/// Model 06_1AH.
///
UINT32 EXTD : 1;
///
/// [Bit 11] APIC Global Enable (R/W).
///
UINT32 EN : 1;
///
/// [Bits 31:12] APIC Base (R/W).
///
UINT32 ApicBase : 20;
///
/// [Bits 63:32] APIC Base (R/W).
///
UINT32 ApicBaseHi : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_APIC_BASE_REGISTER;
/**
Control Features in Intel 64 Processor (R/W). If any one enumeration
condition for defined bit field holds.
@param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
@endcode
@note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
**/
#define MSR_IA32_FEATURE_CONTROL 0x0000003A
/**
MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
/// being written, writes to this bit will result in GP(0). Note: Once the
/// Lock bit is set, the contents of this register cannot be modified.
/// Therefore the lock bit must be set after configuring support for Intel
/// Virtualization Technology and prior to transferring control to an
/// option ROM or the OS. Hence, once the Lock bit is set, the entire
/// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
/// is not deasserted. If any one enumeration condition for defined bit
/// field position greater than bit 0 holds.
///
UINT32 Lock : 1;
///
/// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
/// system executive to use VMX in conjunction with SMX to support
/// Intel(R) Trusted Execution Technology. BIOS must set this bit only
/// when the CPUID function 1 returns VMX feature flag and SMX feature
/// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
/// CPUID.01H:ECX[6] = 1.
///
UINT32 EnableVmxInsideSmx : 1;
///
/// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
/// for system executive that do not require SMX. BIOS must set this bit
/// only when the CPUID function 1 returns VMX feature flag set (ECX bit
/// 5). If CPUID.01H:ECX[5] = 1.
///
UINT32 EnableVmxOutsideSmx : 1;
UINT32 Reserved1 : 5;
///
/// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
/// in the field represents an enable control for a corresponding SENTER
/// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
/// CPUID.01H:ECX[6] = 1.
///
UINT32 SenterLocalFunctionEnables : 7;
///
/// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
/// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
/// 6] is set. If CPUID.01H:ECX[6] = 1.
///
UINT32 SenterGlobalEnable : 1;
UINT32 Reserved2 : 1;
///
/// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
/// enable runtime reconfiguration of SGX Launch Control via
/// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
///
UINT32 SgxLaunchControlEnable : 1;
///
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
/// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
///
UINT32 SgxEnable : 1;
UINT32 Reserved3 : 1;
///
/// [Bit 20] LMCE On (R/WL): When set, system software can program the
/// MSRs associated with LMCE to configure delivery of some machine check
/// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
///
UINT32 LmceOn : 1;
UINT32 Reserved4 : 11;
UINT32 Reserved5 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_FEATURE_CONTROL_REGISTER;
/**
Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
a logical processor. Reset value is Zero. A write to IA32_TSC will modify
the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
not affect the internal invariant TSC hardware.
@param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
@endcode
@note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
**/
#define MSR_IA32_TSC_ADJUST 0x0000003B
/**
BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
microcode update to be loaded into the processor. See Section 9.11.6,
"Microcode Update Loader." A processor may prevent writing to this MSR when
loading guest states on VM entries or saving guest states on VM exits.
Introduced at Display Family / Display Model 06_01H.
@param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = 0;
AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
@endcode
@note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
**/
#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
/**
BIOS Update Signature (RO) Returns the microcode update signature following
the execution of CPUID.01H. A processor may prevent writing to this MSR when
loading guest states on VM entries or saving guest states on VM exits.
Introduced at Display Family / Display Model 06_01H.
@param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
@endcode
@note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
**/
#define MSR_IA32_BIOS_SIGN_ID 0x0000008B
/**
MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
**/
typedef union {
///
/// Individual bit fields
///
struct {
UINT32 Reserved : 32;
///
/// [Bits 63:32] Microcode update signature. This field contains the
/// signature of the currently loaded microcode update when read following
/// the execution of the CPUID instruction, function 1. It is required
/// that this register field be pre-loaded with zero prior to executing
/// the CPUID, function 1. If the field remains equal to zero, then there
/// is no microcode update loaded. Another nonzero value will be the
/// signature.
///
UINT32 MicrocodeUpdateSignature : 32;
} Bits;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_BIOS_SIGN_ID_REGISTER;
/**
IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
default value is the digest of Intel's signing key. Read permitted If
CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
@param ECX MSR_IA32_SGXLEPUBKEYHASHn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
@endcode
@note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
@{
**/
#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
/// @}
/**
SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
1.
@param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
@endcode
@note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
**/
#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
/**
MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
/// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
/// (see Section 34.15.6), the dual-monitor treatment cannot be activated
/// if the bit is 0. This bit is cleared when the logical processor is
/// reset.
///
UINT32 Valid : 1;
UINT32 Reserved1 : 1;
///
/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
/// IA32_VMX_MISC[28].
///
UINT32 BlockSmi : 1;
UINT32 Reserved2 : 9;
///
/// [Bits 31:12] MSEG Base (R/W).
///
UINT32 MsegBase : 20;
UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
/**
MSEG header that is located at the physical address specified by the MsegBase
field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
**/
typedef struct {
///
/// Different processors may use different MSEG revision identifiers. These
/// identifiers enable software to avoid using an MSEG header formatted for
/// one processor on a processor that uses a different format. Software can
/// discover the MSEG revision identifier that a processor uses by reading
/// the VMX capability MSR IA32_VMX_MISC.
//
UINT32 MsegHeaderRevision;
///
/// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
/// is the IA-32e mode SMM feature bit. It indicates whether the logical
/// processor will be in IA-32e mode after the STM is activated.
///
UINT32 MonitorFeatures;
UINT32 GdtrLimit;
UINT32 GdtrBaseOffset;
UINT32 CsSelector;
UINT32 EipOffset;
UINT32 EspOffset;
UINT32 Cr3Offset;
///
/// Pad header so total size is 2KB
///
UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
} MSEG_HEADER;
///
/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
///
#define STM_FEATURES_IA32E 0x1
///
/// @}
///
/**
Base address of the logical processor's SMRAM image (RO, SMM only). If
IA32_VMX_MISC[15].
@param ECX MSR_IA32_SMBASE (0x0000009E)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
@endcode
@note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
**/
#define MSR_IA32_SMBASE 0x0000009E
/**
General Performance Counters (R/W).
MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
@param ECX MSR_IA32_PMCn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_PMC0);
AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
@endcode
@note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
@{
**/
#define MSR_IA32_PMC0 0x000000C1
#define MSR_IA32_PMC1 0x000000C2
#define MSR_IA32_PMC2 0x000000C3
#define MSR_IA32_PMC3 0x000000C4
#define MSR_IA32_PMC4 0x000000C5
#define MSR_IA32_PMC5 0x000000C6
#define MSR_IA32_PMC6 0x000000C7
#define MSR_IA32_PMC7 0x000000C8
/// @}
/**
TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
wrap-around of IA32_APERF.
@param ECX MSR_IA32_MPERF (0x000000E7)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_MPERF);
AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
@endcode
@note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
**/
#define MSR_IA32_MPERF 0x000000E7
/**
Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
the coordinated clock frequency, when the logical processor is in C0.
Cleared upon overflow / wrap-around of IA32_MPERF.
@param ECX MSR_IA32_APERF (0x000000E8)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_APERF);
AsmWriteMsr64 (MSR_IA32_APERF, Msr);
@endcode
@note MSR_IA32_APERF is defined as IA32_APERF in SDM.
**/
#define MSR_IA32_APERF 0x000000E8
/**
MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
Introduced at Display Family / Display Model 06_01H.
@param ECX MSR_IA32_MTRRCAP (0x000000FE)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_MTRRCAP_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_MTRRCAP_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_MTRRCAP_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
@endcode
@note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
**/
#define MSR_IA32_MTRRCAP 0x000000FE
/**
MSR information returned for MSR index #MSR_IA32_MTRRCAP
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] VCNT: The number of variable memory type ranges in the
/// processor.
///
UINT32 VCNT : 8;
///
/// [Bit 8] Fixed range MTRRs are supported when set.
///
UINT32 FIX : 1;
UINT32 Reserved1 : 1;
///
/// [Bit 10] WC Supported when set.
///
UINT32 WC : 1;
///
/// [Bit 11] SMRR Supported when set.
///
UINT32 SMRR : 1;
UINT32 Reserved2 : 20;
UINT32 Reserved3 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_MTRRCAP_REGISTER;
/**
SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@param ECX MSR_IA32_SYSENTER_CS (0x00000174)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_SYSENTER_CS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
@endcode
@note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
**/
#define MSR_IA32_SYSENTER_CS 0x00000174
/**
MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 15:0] CS Selector.
///
UINT32 CS : 16;
UINT32 Reserved1 : 16;
UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_SYSENTER_CS_REGISTER;
/**
SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
@endcode
@note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
**/
#define MSR_IA32_SYSENTER_ESP 0x00000175
/**
SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
@param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
@endcode
@note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
**/
#define MSR_IA32_SYSENTER_EIP 0x00000176
/**
Global Machine Check Capability (RO). Introduced at Display Family / Display
Model 06_01H.
@param ECX MSR_IA32_MCG_CAP (0x00000179)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_MCG_CAP_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_MCG_CAP_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_MCG_CAP_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
@endcode
@note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
**/
#define MSR_IA32_MCG_CAP 0x00000179
/**
MSR information returned for MSR index #MSR_IA32_MCG_CAP
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Count: Number of reporting banks.
///
UINT32 Count : 8;
///
/// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
///
UINT32 MCG_CTL_P : 1;
///
/// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
/// if this bit is set.
///
UINT32 MCG_EXT_P : 1;
///
/// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
/// Introduced at Display Family / Display Model 06_01H.
///
UINT32 MCP_CMCI_P : 1;
///
/// [Bit 11] MCG_TES_P: Threshold-based error status register are present
/// if this bit is set.
///
UINT32 MCG_TES_P : 1;
UINT32 Reserved1 : 4;
///
/// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
/// registers present.
///
UINT32 MCG_EXT_CNT : 8;
///
/// [Bit 24] MCG_SER_P: The processor supports software error recovery if
/// this bit is set.
///
UINT32 MCG_SER_P : 1;
UINT32 Reserved2 : 1;
///
/// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
/// firmware to be invoked when an error is detected so that it may
/// provide additional platform specific information in an ACPI format
/// "Generic Error Data Entry" that augments the data included in machine
/// check bank registers. Introduced at Display Family / Display Model
/// 06_3EH.
///
UINT32 MCG_ELOG_P : 1;
///
/// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
/// state in IA32_MCG_STATUS and associated MSR necessary to configure
/// Local Machine Check Exception (LMCE). Introduced at Display Family /
/// Display Model 06_3EH.
///
UINT32 MCG_LMCE_P : 1;
UINT32 Reserved3 : 4;
UINT32 Reserved4 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_MCG_CAP_REGISTER;
/**
Global Machine Check Status (R/W0). Introduced at Display Family / Display
Model 06_01H.
@param ECX MSR_IA32_MCG_STATUS (0x0000017A)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_MCG_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_MCG_STATUS_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_MCG_STATUS_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
@endcode
@note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
**/
#define MSR_IA32_MCG_STATUS 0x0000017A
/**
MSR information returned for MSR index #MSR_IA32_MCG_STATUS
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
/// Model 06_01H.
///
UINT32 RIPV : 1;
///
/// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
/// Model 06_01H.
///
UINT32 EIPV : 1;
///
/// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
/// / Display Model 06_01H.
///
UINT32 MCIP : 1;
///
/// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
///
UINT32 LMCE_S : 1;
UINT32 Reserved1 : 28;
UINT32 Reserved2 : 32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_MCG_STATUS_REGISTER;
/**
Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
@param ECX MSR_IA32_MCG_CTL (0x0000017B)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
@endcode
@note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
**/
#define MSR_IA32_MCG_CTL 0x0000017B
/**
Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
@param ECX MSR_IA32_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_PERFEVTSEL_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
@endcode
@note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
@{
**/
#define MSR_IA32_PERFEVTSEL0 0x00000186
#define MSR_IA32_PERFEVTSEL1 0x00000187
#define MSR_IA32_PERFEVTSEL2 0x00000188
#define MSR_IA32_PERFEVTSEL3 0x00000189
/// @}
/**
MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
#MSR_IA32_PERFEVTSEL3
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bits 7:0] Event Select: Selects a performance event logic unit.
///
UINT32 EventSelect : 8;
///
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
/// detect on the selected event logic.
///
UINT32 UMASK : 8;
///
/// [Bit 16] USR: Counts while in privilege level is not ring 0.
///
UINT32 USR : 1;
///
/// [Bit 17] OS: Counts while in privilege level is ring 0.
///
UINT32 OS : 1;
///
/// [Bit 18] Edge: Enables edge detection if set.
///
UINT32 E : 1;
///
/// [Bit 19] PC: enables pin control.
///
UINT32 PC : 1;
///
/// [Bit 20] INT: enables interrupt on counter overflow.