From 8c8a940273ee275d9a8349052427a7e691cf29d0 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Fri, 19 Jan 2024 14:30:18 +0000 Subject: [PATCH] Use insGetPredicateType for SVE encodings (#97142) * Use insGetPredicateType for SVE encodings * Add predicate as counter printing * Pass type to emitPredicateRegName --- src/coreclr/jit/emitarm64.cpp | 193 +++++++++++++++++++--------------- src/coreclr/jit/emitarm64.h | 14 +-- 2 files changed, 114 insertions(+), 93 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 1877f0a9036e9..5c9fb990bb859 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -1930,6 +1930,14 @@ static const char * const pRegNames[] = "p10", "p11", "p12", "p13", "p14", "p15" }; + +static const char * const pnRegNames[] = +{ + "pn0", "pn1", "pn2", "pn3", "pn4", + "pn5", "pn6", "pn7", "pn8", "pn9", + "pn10", "pn11", "pn12", "pn13", "pn14", + "pn15" +}; // clang-format on //------------------------------------------------------------------------ @@ -2027,13 +2035,13 @@ const char* emitter::emitVectorRegName(regNumber reg) // Return value: // A string that represents a predicate register name. // -const char* emitter::emitPredicateRegName(regNumber reg) +const char* emitter::emitPredicateRegName(regNumber reg, PredicateType ptype) { assert((reg >= REG_P0) && (reg <= REG_P15)); int index = (int)reg - (int)REG_P0; - return pRegNames[index]; + return (ptype == PREDICATE_N_SIZED) ? pnRegNames[index] : pRegNames[index]; } /***************************************************************************** @@ -14065,7 +14073,7 @@ void emitter::emitIns_Call(EmitCallType callType, * Returns the predicate type for the given SVE format. */ -/*static*/ emitter::PredicateType emitter::insGetPredicateType(insFormat fmt) +/*static*/ emitter::PredicateType emitter::insGetPredicateType(insFormat fmt, int regpos /* =0 */) { switch (fmt) { @@ -14107,13 +14115,8 @@ void emitter::emitIns_Call(EmitCallType callType, case IF_SVE_IF_4A_A: case IF_SVE_IM_3A: case IF_SVE_IN_4A: - case IF_SVE_CX_4A: - case IF_SVE_CX_4A_A: - case IF_SVE_CY_3A: - case IF_SVE_CY_3B: case IF_SVE_IX_4A: case IF_SVE_HI_3A: - case IF_SVE_HT_4A: case IF_SVE_DG_2A: case IF_SVE_IO_3A: case IF_SVE_IP_4A: @@ -14124,7 +14127,6 @@ void emitter::emitIns_Call(EmitCallType callType, case IF_SVE_DA_4A: case IF_SVE_DB_3B: case IF_SVE_DC_3A: - case IF_SVE_GE_4A: case IF_SVE_GI_4A: case IF_SVE_IC_3A_C: case IF_SVE_IC_3A: @@ -14197,21 +14199,29 @@ void emitter::emitIns_Call(EmitCallType callType, case IF_SVE_CF_2C: case IF_SVE_CF_2D: case IF_SVE_CI_3A: - case IF_SVE_DL_2A: case IF_SVE_DM_2A: case IF_SVE_DN_2A: case IF_SVE_DO_2A: case IF_SVE_DP_2A: + case IF_SVE_DR_1A: + case IF_SVE_DT_3A: + case IF_SVE_DU_3A: case IF_SVE_CK_2A: case IF_SVE_DI_2A: return PREDICATE_SIZED; + case IF_SVE_DL_2A: + case IF_SVE_DY_3A: + case IF_SVE_DZ_1A: + return PREDICATE_N_SIZED; + // This is a special case as the second register could be ZERO or MERGE. // / // Therefore, by default return NONE due to ambiguity. case IF_SVE_AH_3A: case IF_SVE_DB_3A: // TODO: Handle these cases. + assert(false); break; case IF_SVE_JD_4B: @@ -14274,6 +14284,15 @@ void emitter::emitIns_Call(EmitCallType callType, case IF_SVE_IY_4A: return PREDICATE_NONE; + case IF_SVE_CX_4A: + case IF_SVE_CX_4A_A: + case IF_SVE_CY_3A: + case IF_SVE_CY_3B: + case IF_SVE_GE_4A: + case IF_SVE_HT_4A: + assert((regpos == 1) || (regpos == 2)); + return (regpos == 1 ? PREDICATE_SIZED : PREDICATE_ZERO); + default: break; } @@ -17502,7 +17521,7 @@ void emitter::emitDispSveConsecutiveRegList(regNumber firstReg, unsigned listSiz void emitter::emitDispPredicateReg(regNumber reg, PredicateType ptype, insOpts opt, bool addComma) { assert(isPredicateRegister(reg)); - printf(emitPredicateRegName(reg)); + printf(emitPredicateRegName(reg, ptype)); if (ptype == PREDICATE_MERGE) { @@ -17512,7 +17531,7 @@ void emitter::emitDispPredicateReg(regNumber reg, PredicateType ptype, insOpts o { printf("/z"); } - else if (ptype == PREDICATE_SIZED) + else if (ptype == PREDICATE_SIZED || ptype == PREDICATE_N_SIZED) { emitDispElemsize(optGetSveElemsize(opt)); } @@ -19188,10 +19207,10 @@ void emitter::emitDispInsHelp( // (predicated) case IF_SVE_GR_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 floating-point pairwise operations case IF_SVE_HL_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point arithmetic (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., /, . @@ -19206,18 +19225,18 @@ void emitter::emitDispInsHelp( // ., /M, ., # case IF_SVE_AM_2A: // ........xx...... ...gggxxiiiddddd -- SVE bitwise shift by immediate (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispImm(emitGetInsSC(id), false); // iiii + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispImm(emitGetInsSC(id), false); // iiii break; // ., /M, ., .D case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispSveReg(id->idReg3(), INS_OPTS_SCALABLE_D, false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispSveReg(id->idReg3(), INS_OPTS_SCALABLE_D, false); // mmmmm break; // ., /M, ., . @@ -19226,8 +19245,8 @@ void emitter::emitDispInsHelp( // (predicated) case IF_SVE_AS_4A: // ........xx.mmmmm ...gggaaaaaddddd -- SVE integer multiply-add writing multiplicand // (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg emitDispSveReg(id->idReg3(), id->idInsOpt(), true); emitDispSveReg(id->idReg4(), id->idInsOpt(), false); break; @@ -19260,10 +19279,10 @@ void emitter::emitDispInsHelp( // ., , ., . case IF_SVE_CM_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // , , , . @@ -19271,10 +19290,10 @@ void emitter::emitDispInsHelp( case IF_SVE_CN_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register case IF_SVE_HJ_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispReg(id->idReg1(), size, true); // ddddd + emitDispLowPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispReg(id->idReg1(), size, true); // ddddd + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // , , . @@ -19284,9 +19303,9 @@ void emitter::emitDispInsHelp( case IF_SVE_CR_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to SIMD&FP scalar register case IF_SVE_CS_3A: // ........xx...... ...gggnnnnnddddd -- SVE extract element to general register case IF_SVE_HE_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispReg(id->idReg1(), size, true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., , . @@ -19295,15 +19314,15 @@ void emitter::emitDispInsHelp( case IF_SVE_AL_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer min/max reduction (quadwords) case IF_SVE_GS_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point recursive reduction (quadwords) emitDispVectorReg(id->idReg1(), optSveToQuadwordElemsizeArrangement(id->idInsOpt()), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; //
, , . case IF_SVE_AI_3A: // ........xx...... ...gggnnnnnddddd -- SVE integer add reduction (predicated) - emitDispReg(id->idReg1(), EA_8BYTE, true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispReg(id->idReg1(), EA_8BYTE, true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., /M, . @@ -19313,65 +19332,65 @@ void emitter::emitDispInsHelp( case IF_SVE_ES_3A: // ........xx...... ...gggnnnnnddddd -- SVE2 integer unary operations (predicated) case IF_SVE_HQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point round to integral value case IF_SVE_HR_3A: // ........xx...... ...gggnnnnnddddd -- SVE floating-point unary operations - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., , . case IF_SVE_CL_3A: // ........xx...... ...gggnnnnnddddd -- SVE compress active elements - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; // ., /M, case IF_SVE_CP_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy SIMD&FP scalar register to vector // (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg - emitDispReg(id->idReg3(), size, false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispReg(id->idReg3(), size, false); // mmmmm break; // ., /M, case IF_SVE_CQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE copy general register to vector (predicated) - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg - emitDispReg(encodingZRtoSP(id->idReg3()), size, false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispReg(encodingZRtoSP(id->idReg3()), size, false); // mmmmm break; // ., /Z, ., . case IF_SVE_CX_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors case IF_SVE_GE_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE2 character match case IF_SVE_HT_4A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE floating-point compare vectors - emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD - emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // nnnnn - emitDispSveReg(id->idReg4(), id->idInsOpt(), false); // mmmmm + emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt, 1), id->idInsOpt(), true); // DDDD + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt, 2), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // nnnnn + emitDispSveReg(id->idReg4(), id->idInsOpt(), false); // mmmmm break; // ., /Z, ., .D case IF_SVE_CX_4A_A: // ........xx.mmmmm ...gggnnnnn.DDDD -- SVE integer compare vectors - emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD - emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // nnnnn - emitDispSveReg(id->idReg4(), INS_OPTS_SCALABLE_D, false); // mmmmm + emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt, 1), id->idInsOpt(), true); // DDDD + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt, 2), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // nnnnn + emitDispSveReg(id->idReg4(), INS_OPTS_SCALABLE_D, false); // mmmmm break; // ., /Z, ., # case IF_SVE_CY_3A: // ........xx.iiiii ...gggnnnnn.DDDD -- SVE integer compare with signed immediate case IF_SVE_CY_3B: // ........xx.iiiii ii.gggnnnnn.DDDD -- SVE integer compare with unsigned immediate - emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD - emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // nnnnn - emitDispImm(emitGetInsSC(id), false, (fmt == IF_SVE_CY_3B)); // iiiii + emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt, 1), id->idInsOpt(), true); // DDDD + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt, 2), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), id->idInsOpt(), true); // nnnnn + emitDispImm(emitGetInsSC(id), false, (fmt == IF_SVE_CY_3B)); // iiiii break; // ., /M, . case IF_SVE_EQ_3A: // ........xx...... ...gggnnnnnddddd -- SVE2 integer pairwise add and accumulate long - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispLowPredicateReg(id->idReg2(), PREDICATE_MERGE, id->idInsOpt(), true); // ggg - emitDispSveReg(id->idReg3(), (insOpts)((unsigned)id->idInsOpt() - 1), false); // mmmmm + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispLowPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // ggg + emitDispSveReg(id->idReg3(), (insOpts)((unsigned)id->idInsOpt() - 1), false); // mmmmm break; // .H, { .S-.S }, # @@ -19383,22 +19402,22 @@ void emitter::emitDispInsHelp( // , ., case IF_SVE_DL_2A: // ........xx...... .....l.NNNNddddd -- SVE predicate count (predicate-as-counter) - emitDispReg(id->idReg1(), id->idOpSize(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_SIZED, id->idInsOpt(), true); // NNNN + emitDispReg(id->idReg1(), id->idOpSize(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), true); // NNNN emitDispVectorLengthSpecifier(id); break; // , . case IF_SVE_DM_2A: // ........xx...... .......MMMMddddd -- SVE inc/dec register by predicate count - emitDispReg(id->idReg1(), id->idOpSize(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_SIZED, id->idInsOpt(), false); // MMMM + emitDispReg(id->idReg1(), id->idOpSize(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), false); // MMMM break; // ., . case IF_SVE_DN_2A: // ........xx...... .......MMMMddddd -- SVE inc/dec vector by predicate count case IF_SVE_DP_2A: // ........xx...... .......MMMMddddd -- SVE saturating inc/dec vector by predicate count - emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_SIZED, id->idInsOpt(), false); // MMMM + emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), false); // MMMM break; // , ., @@ -19408,9 +19427,9 @@ void emitter::emitDispInsHelp( { // 32-bit result: , ., // 64-bit result: , . - const bool is32BitResult = (id->idOpSize() == EA_4BYTE); // X - emitDispReg(id->idReg1(), EA_8BYTE, true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_SIZED, id->idInsOpt(), is32BitResult); // MMMM + const bool is32BitResult = (id->idOpSize() == EA_4BYTE); // X + emitDispReg(id->idReg1(), EA_8BYTE, true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), is32BitResult); // MMMM if (is32BitResult) { @@ -19420,8 +19439,8 @@ void emitter::emitDispInsHelp( else { assert((ins == INS_sve_uqdecp) || (ins == INS_sve_uqincp)); - emitDispReg(id->idReg1(), id->idOpSize(), true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_SIZED, id->idInsOpt(), false); // MMMM + emitDispReg(id->idReg1(), id->idOpSize(), true); // ddddd + emitDispPredicateReg(id->idReg2(), insGetPredicateType(fmt), id->idInsOpt(), false); // MMMM } break; @@ -19431,7 +19450,7 @@ void emitter::emitDispInsHelp( // .B case IF_SVE_DR_1A: // ................ .......NNNN..... -- SVE FFR write from predicate - emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), false); // NNNN + emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), id->idInsOpt(), false); // NNNN break; // , @@ -19464,9 +19483,9 @@ void emitter::emitDispInsHelp( case IF_SVE_DT_3A: // ........xx.mmmmm ...X..nnnnn.DDDD -- SVE integer compare scalar count and limit // ., , case IF_SVE_DU_3A: // ........xx.mmmmm ......nnnnn.DDDD -- SVE pointer conflict compare - emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD - emitDispReg(id->idReg2(), id->idOpSize(), true); // nnnnn - emitDispReg(id->idReg3(), id->idOpSize(), false); // mmmmm + emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), id->idInsOpt(), true); // DDDD + emitDispReg(id->idReg2(), id->idOpSize(), true); // nnnnn + emitDispReg(id->idReg3(), id->idOpSize(), false); // mmmmm break; // {., .}, , @@ -19480,15 +19499,15 @@ void emitter::emitDispInsHelp( // ., , , case IF_SVE_DY_3A: // ........xx.mmmmm ..l...nnnnn..DDD -- SVE integer compare scalar count and limit // (predicate-as-counter) - emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDD - emitDispReg(id->idReg2(), id->idOpSize(), true); // nnnnn - emitDispReg(id->idReg3(), id->idOpSize(), true); // mmmmm + emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), id->idInsOpt(), true); // DDD + emitDispReg(id->idReg2(), id->idOpSize(), true); // nnnnn + emitDispReg(id->idReg3(), id->idOpSize(), true); // mmmmm emitDispVectorLengthSpecifier(id); break; // PTRUE . case IF_SVE_DZ_1A: // ........xx...... .............DDD -- sve_int_pn_ptrue - emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), false); // DDD + emitDispPredicateReg(id->idReg1(), insGetPredicateType(fmt), id->idInsOpt(), false); // DDD break; // FDUP ., # diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index e76290a28a28b..04f8322a06fc9 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -21,15 +21,16 @@ static bool strictArmAsm; enum PredicateType { - PREDICATE_NONE = 0, - PREDICATE_MERGE, - PREDICATE_ZERO, - PREDICATE_SIZED, + PREDICATE_NONE = 0, // Predicate printed with no extensions + PREDICATE_MERGE, // Predicate printed with /m + PREDICATE_ZERO, // Predicate printed with /z + PREDICATE_SIZED, // Predicate printed with element size + PREDICATE_N_SIZED, // Predicate printed printed as counter with element size }; const char* emitSveRegName(regNumber reg); const char* emitVectorRegName(regNumber reg); -const char* emitPredicateRegName(regNumber reg); +const char* emitPredicateRegName(regNumber reg, PredicateType ptype); void emitDispInsHelp( instrDesc* id, bool isNew, bool doffs, bool asmfm, unsigned offset, BYTE* pCode, size_t sz, insGroup* ig); @@ -491,7 +492,8 @@ static code_t insEncodeSveElemsize_tszh_22_tszl_20_to_19(emitAttr size); static int insGetSveReg1ListSize(instruction ins); // Returns the predicate type for the given SVE format. -static PredicateType insGetPredicateType(insFormat fmt); +// Register position is required for instructions with multiple predicates. +static PredicateType insGetPredicateType(insFormat fmt, int regpos = 0); // Returns true if the specified instruction can encode the 'dtype' field. static bool canEncodeSveElemsize_dtype(instruction ins);