Database of CPU Opcodes
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Updated
Feb 18, 2024 - Python
Database of CPU Opcodes
RISC-V Assembly code assembler package for Python.
Instruction Set Architecture Description Format
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A modular general 2-pass assembler written in Python.
18-bit processor implementation using Logisim
This is the implementation of an instruction-set architecture (ISA) simulator in Python. It deals with small machine language programs in order to understand the functionality and the structure of a simple processor.
Python implementation of a 32-bit processor with its own ISA (Instruction Set Architecture)
A 64-bit stack based instruction set architecture definition with reference implementation. (The assembler is part of my C compiler that targets StackVM)
Mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's registers
SUTD ISTD 2020 Computation Structures Electronic Hardware 1D Project
Testing out optimal magic numbers for the old fast inverse square root function.
A assembler and simulator for a custom RISC ISA
A small toy VM and assembler written in python as a learning exercise. Has 3 registers, with storage, maths and printing.
Assembler implementation or the Hack computer from the Nand To Tetris course.
An 8-bit ISA and CPU implementation in Minecraft.
Converts LEGv8 instructions to Machine Code
SAR: Simple Architecture RISC Simulator
synacor challenge
SEA-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.
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