Test suite designed to check compliance with the SystemVerilog standard.

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.

Funtional verification for darkriscv.

This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.

Here you'll find the game "Donkey Kong" written 100% in SysVerilog. You'll need an FPGA card, a screen, a keyboard, and audio devices for the full functionality.

Методические материалы по разработке процессора архитектуры RISC-V

A reimplementation of the Bitcoin hash, both in parallel and serial

DUTH RISC-V Microprocessor

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

Kernel Image Convolution using SystemVerilog

Fixed point math library for SystemVerilog

A Reconfigurable Image Acqusition and Prosessing Subsystem in SystemVerilog.

Design of a Vending Machine using SystemVerilog

ZCU104 Photonic Machine Learning Code Implemenation. It is composed of verilog codes and python codes.