An algorithm, developed in Verilog hardware design language (HDL), that encrypts a text input into binary, then decrypts it back, using logic gates and public/private keys. This system was developed as a Logical Systems subject exercise (UFMG).
An algorithm, developed in Verilog hardware design language (HDL), that implements a Johnson Counter, which counts 2n states if the number of bits is n. This system was developed as a Logical Systems subject exercise (UFMG).
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