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smsc95xx.c
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smsc95xx.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
*
* Copyright (C) 2007-2008 SMSC
*
*****************************************************************************/
#include <linux/module.h>
#include <linux/kmod.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/usb.h>
#include <linux/bitrev.h>
#include <linux/crc16.h>
#include <linux/crc32.h>
#include <linux/usb/usbnet.h>
#include <linux/slab.h>
#include <linux/of_net.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mdio.h>
#include <linux/phy.h>
#include <net/selftests.h>
#include "smsc95xx.h"
#define SMSC_CHIPNAME "smsc95xx"
#define SMSC_DRIVER_VERSION "2.0.0"
#define HS_USB_PKT_SIZE (512)
#define FS_USB_PKT_SIZE (64)
#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
#define DEFAULT_BULK_IN_DELAY (0x00002000)
#define MAX_SINGLE_PACKET_SIZE (2048)
#define LAN95XX_EEPROM_MAGIC (0x9500)
#define EEPROM_MAC_OFFSET (0x01)
#define DEFAULT_TX_CSUM_ENABLE (true)
#define DEFAULT_RX_CSUM_ENABLE (true)
#define SMSC95XX_INTERNAL_PHY_ID (1)
#define SMSC95XX_TX_OVERHEAD (8)
#define SMSC95XX_TX_OVERHEAD_CSUM (12)
#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
#define FEATURE_8_WAKEUP_FILTERS (0x01)
#define FEATURE_PHY_NLP_CROSSOVER (0x02)
#define FEATURE_REMOTE_WAKEUP (0x04)
#define SUSPEND_SUSPEND0 (0x01)
#define SUSPEND_SUSPEND1 (0x02)
#define SUSPEND_SUSPEND2 (0x04)
#define SUSPEND_SUSPEND3 (0x08)
#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
#define SMSC95XX_NR_IRQS (1) /* raise to 12 for GPIOs */
#define PHY_HWIRQ (SMSC95XX_NR_IRQS - 1)
struct smsc95xx_priv {
u32 mac_cr;
u32 hash_hi;
u32 hash_lo;
u32 wolopts;
spinlock_t mac_cr_lock;
u8 features;
u8 suspend_flags;
bool is_internal_phy;
struct irq_chip irqchip;
struct irq_domain *irqdomain;
struct fwnode_handle *irqfwnode;
struct mii_bus *mdiobus;
struct phy_device *phydev;
struct task_struct *pm_task;
};
static bool turbo_mode = true;
module_param(turbo_mode, bool, 0644);
MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
u32 *data)
{
struct smsc95xx_priv *pdata = dev->driver_priv;
u32 buf;
int ret;
int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
if (current != pdata->pm_task)
fn = usbnet_read_cmd;
else
fn = usbnet_read_cmd_nopm;
ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
| USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, index, &buf, 4);
if (ret < 4) {
ret = ret < 0 ? ret : -ENODATA;
if (ret != -ENODEV)
netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
index, ret);
return ret;
}
le32_to_cpus(&buf);
*data = buf;
return ret;
}
static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
u32 data)
{
struct smsc95xx_priv *pdata = dev->driver_priv;
u32 buf;
int ret;
int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
if (current != pdata->pm_task)
fn = usbnet_write_cmd;
else
fn = usbnet_write_cmd_nopm;
buf = data;
cpu_to_le32s(&buf);
ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
| USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, index, &buf, 4);
if (ret < 0 && ret != -ENODEV)
netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
index, ret);
return ret;
}
/* Loop until the read is completed with timeout
* called with phy_mutex held */
static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev)
{
unsigned long start_time = jiffies;
u32 val;
int ret;
do {
ret = smsc95xx_read_reg(dev, MII_ADDR, &val);
if (ret < 0) {
/* Ignore -ENODEV error during disconnect() */
if (ret == -ENODEV)
return 0;
netdev_warn(dev->net, "Error reading MII_ACCESS\n");
return ret;
}
if (!(val & MII_BUSY_))
return 0;
} while (!time_after(jiffies, start_time + HZ));
return -EIO;
}
static u32 mii_address_cmd(int phy_id, int idx, u16 op)
{
return (phy_id & 0x1f) << 11 | (idx & 0x1f) << 6 | op;
}
static int smsc95xx_mdio_read(struct usbnet *dev, int phy_id, int idx)
{
u32 val, addr;
int ret;
mutex_lock(&dev->phy_mutex);
/* confirm MII not busy */
ret = smsc95xx_phy_wait_not_busy(dev);
if (ret < 0) {
netdev_warn(dev->net, "%s: MII is busy\n", __func__);
goto done;
}
/* set the address, index & direction (read from PHY) */
addr = mii_address_cmd(phy_id, idx, MII_READ_ | MII_BUSY_);
ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
if (ret < 0) {
if (ret != -ENODEV)
netdev_warn(dev->net, "Error writing MII_ADDR\n");
goto done;
}
ret = smsc95xx_phy_wait_not_busy(dev);
if (ret < 0) {
netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
goto done;
}
ret = smsc95xx_read_reg(dev, MII_DATA, &val);
if (ret < 0) {
if (ret != -ENODEV)
netdev_warn(dev->net, "Error reading MII_DATA\n");
goto done;
}
ret = (u16)(val & 0xFFFF);
done:
mutex_unlock(&dev->phy_mutex);
/* Ignore -ENODEV error during disconnect() */
if (ret == -ENODEV)
return 0;
return ret;
}
static void smsc95xx_mdio_write(struct usbnet *dev, int phy_id, int idx,
int regval)
{
u32 val, addr;
int ret;
mutex_lock(&dev->phy_mutex);
/* confirm MII not busy */
ret = smsc95xx_phy_wait_not_busy(dev);
if (ret < 0) {
netdev_warn(dev->net, "%s: MII is busy\n", __func__);
goto done;
}
val = regval;
ret = smsc95xx_write_reg(dev, MII_DATA, val);
if (ret < 0) {
if (ret != -ENODEV)
netdev_warn(dev->net, "Error writing MII_DATA\n");
goto done;
}
/* set the address, index & direction (write to PHY) */
addr = mii_address_cmd(phy_id, idx, MII_WRITE_ | MII_BUSY_);
ret = smsc95xx_write_reg(dev, MII_ADDR, addr);
if (ret < 0) {
if (ret != -ENODEV)
netdev_warn(dev->net, "Error writing MII_ADDR\n");
goto done;
}
ret = smsc95xx_phy_wait_not_busy(dev);
if (ret < 0) {
netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
goto done;
}
done:
mutex_unlock(&dev->phy_mutex);
}
static int smsc95xx_mdiobus_reset(struct mii_bus *bus)
{
struct smsc95xx_priv *pdata;
struct usbnet *dev;
u32 val;
int ret;
dev = bus->priv;
pdata = dev->driver_priv;
if (pdata->is_internal_phy)
return 0;
mutex_lock(&dev->phy_mutex);
ret = smsc95xx_read_reg(dev, PM_CTRL, &val);
if (ret < 0)
goto reset_out;
val |= PM_CTL_PHY_RST_;
ret = smsc95xx_write_reg(dev, PM_CTRL, val);
if (ret < 0)
goto reset_out;
/* Driver has no knowledge at this point about the external PHY.
* The 802.3 specifies that the reset process shall
* be completed within 0.5 s.
*/
fsleep(500000);
reset_out:
mutex_unlock(&dev->phy_mutex);
return 0;
}
static int smsc95xx_mdiobus_read(struct mii_bus *bus, int phy_id, int idx)
{
struct usbnet *dev = bus->priv;
return smsc95xx_mdio_read(dev, phy_id, idx);
}
static int smsc95xx_mdiobus_write(struct mii_bus *bus, int phy_id, int idx,
u16 regval)
{
struct usbnet *dev = bus->priv;
smsc95xx_mdio_write(dev, phy_id, idx, regval);
return 0;
}
static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
{
unsigned long start_time = jiffies;
u32 val;
int ret;
do {
ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
if (ret < 0) {
netdev_warn(dev->net, "Error reading E2P_CMD\n");
return ret;
}
if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
break;
udelay(40);
} while (!time_after(jiffies, start_time + HZ));
if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
netdev_warn(dev->net, "EEPROM read operation timeout\n");
return -EIO;
}
return 0;
}
static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
{
unsigned long start_time = jiffies;
u32 val;
int ret;
do {
ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
if (ret < 0) {
netdev_warn(dev->net, "Error reading E2P_CMD\n");
return ret;
}
if (!(val & E2P_CMD_BUSY_))
return 0;
udelay(40);
} while (!time_after(jiffies, start_time + HZ));
netdev_warn(dev->net, "EEPROM is busy\n");
return -EIO;
}
static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
u8 *data)
{
u32 val;
int i, ret;
BUG_ON(!dev);
BUG_ON(!data);
ret = smsc95xx_eeprom_confirm_not_busy(dev);
if (ret)
return ret;
for (i = 0; i < length; i++) {
val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
if (ret < 0) {
netdev_warn(dev->net, "Error writing E2P_CMD\n");
return ret;
}
ret = smsc95xx_wait_eeprom(dev);
if (ret < 0)
return ret;
ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
if (ret < 0) {
netdev_warn(dev->net, "Error reading E2P_DATA\n");
return ret;
}
data[i] = val & 0xFF;
offset++;
}
return 0;
}
static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
u8 *data)
{
u32 val;
int i, ret;
BUG_ON(!dev);
BUG_ON(!data);
ret = smsc95xx_eeprom_confirm_not_busy(dev);
if (ret)
return ret;
/* Issue write/erase enable command */
val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
if (ret < 0) {
netdev_warn(dev->net, "Error writing E2P_DATA\n");
return ret;
}
ret = smsc95xx_wait_eeprom(dev);
if (ret < 0)
return ret;
for (i = 0; i < length; i++) {
/* Fill data register */
val = data[i];
ret = smsc95xx_write_reg(dev, E2P_DATA, val);
if (ret < 0) {
netdev_warn(dev->net, "Error writing E2P_DATA\n");
return ret;
}
/* Send "write" command */
val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
ret = smsc95xx_write_reg(dev, E2P_CMD, val);
if (ret < 0) {
netdev_warn(dev->net, "Error writing E2P_CMD\n");
return ret;
}
ret = smsc95xx_wait_eeprom(dev);
if (ret < 0)
return ret;
offset++;
}
return 0;
}
static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
u32 data)
{
const u16 size = 4;
u32 buf;
int ret;
buf = data;
cpu_to_le32s(&buf);
ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
USB_DIR_OUT | USB_TYPE_VENDOR |
USB_RECIP_DEVICE,
0, index, &buf, size);
if (ret < 0)
netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
ret);
return ret;
}
/* returns hash bit number for given MAC address
* example:
* 01 00 5E 00 00 01 -> returns bit number 31 */
static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
{
return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
}
static void smsc95xx_set_multicast(struct net_device *netdev)
{
struct usbnet *dev = netdev_priv(netdev);
struct smsc95xx_priv *pdata = dev->driver_priv;
unsigned long flags;
int ret;
pdata->hash_hi = 0;
pdata->hash_lo = 0;
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
if (dev->net->flags & IFF_PROMISC) {
netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
pdata->mac_cr |= MAC_CR_PRMS_;
pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
} else if (dev->net->flags & IFF_ALLMULTI) {
netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
pdata->mac_cr |= MAC_CR_MCPAS_;
pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
} else if (!netdev_mc_empty(dev->net)) {
struct netdev_hw_addr *ha;
pdata->mac_cr |= MAC_CR_HPFILT_;
pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
netdev_for_each_mc_addr(ha, netdev) {
u32 bitnum = smsc95xx_hash(ha->addr);
u32 mask = 0x01 << (bitnum & 0x1F);
if (bitnum & 0x20)
pdata->hash_hi |= mask;
else
pdata->hash_lo |= mask;
}
netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
pdata->hash_hi, pdata->hash_lo);
} else {
netif_dbg(dev, drv, dev->net, "receive own packets only\n");
pdata->mac_cr &=
~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
}
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
/* Initiate async writes, as we can't wait for completion here */
ret = smsc95xx_write_reg_async(dev, HASHH, pdata->hash_hi);
if (ret < 0)
netdev_warn(dev->net, "failed to initiate async write to HASHH\n");
ret = smsc95xx_write_reg_async(dev, HASHL, pdata->hash_lo);
if (ret < 0)
netdev_warn(dev->net, "failed to initiate async write to HASHL\n");
ret = smsc95xx_write_reg_async(dev, MAC_CR, pdata->mac_cr);
if (ret < 0)
netdev_warn(dev->net, "failed to initiate async write to MAC_CR\n");
}
static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev)
{
u32 flow = 0, afc_cfg;
struct smsc95xx_priv *pdata = dev->driver_priv;
bool tx_pause, rx_pause;
int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
if (ret < 0)
return ret;
if (pdata->phydev->duplex == DUPLEX_FULL) {
phy_get_pause(pdata->phydev, &tx_pause, &rx_pause);
if (rx_pause)
flow = 0xFFFF0002;
if (tx_pause) {
afc_cfg |= 0xF;
flow |= 0xFFFF0000;
} else {
afc_cfg &= ~0xF;
}
netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
rx_pause ? "enabled" : "disabled",
tx_pause ? "enabled" : "disabled");
} else {
netif_dbg(dev, link, dev->net, "half duplex\n");
afc_cfg |= 0xF;
}
ret = smsc95xx_write_reg(dev, FLOW, flow);
if (ret < 0)
return ret;
return smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
}
static void smsc95xx_mac_update_fullduplex(struct usbnet *dev)
{
struct smsc95xx_priv *pdata = dev->driver_priv;
unsigned long flags;
int ret;
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
if (pdata->phydev->duplex != DUPLEX_FULL) {
pdata->mac_cr &= ~MAC_CR_FDPX_;
pdata->mac_cr |= MAC_CR_RCVOWN_;
} else {
pdata->mac_cr &= ~MAC_CR_RCVOWN_;
pdata->mac_cr |= MAC_CR_FDPX_;
}
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
if (ret < 0) {
if (ret != -ENODEV)
netdev_warn(dev->net,
"Error updating MAC full duplex mode\n");
return;
}
ret = smsc95xx_phy_update_flowcontrol(dev);
if (ret < 0)
netdev_warn(dev->net, "Error updating PHY flow control\n");
}
static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
{
struct smsc95xx_priv *pdata = dev->driver_priv;
unsigned long flags;
u32 intdata;
if (urb->actual_length != 4) {
netdev_warn(dev->net, "unexpected urb length %d\n",
urb->actual_length);
return;
}
intdata = get_unaligned_le32(urb->transfer_buffer);
netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
local_irq_save(flags);
if (intdata & INT_ENP_PHY_INT_)
generic_handle_domain_irq(pdata->irqdomain, PHY_HWIRQ);
else
netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
intdata);
local_irq_restore(flags);
}
/* Enable or disable Tx & Rx checksum offload engines */
static int smsc95xx_set_features(struct net_device *netdev,
netdev_features_t features)
{
struct usbnet *dev = netdev_priv(netdev);
u32 read_buf;
int ret;
ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
if (ret < 0)
return ret;
if (features & NETIF_F_IP_CSUM)
read_buf |= Tx_COE_EN_;
else
read_buf &= ~Tx_COE_EN_;
if (features & NETIF_F_RXCSUM)
read_buf |= Rx_COE_EN_;
else
read_buf &= ~Rx_COE_EN_;
ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
if (ret < 0)
return ret;
netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
return 0;
}
static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
{
return MAX_EEPROM_SIZE;
}
static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
struct ethtool_eeprom *ee, u8 *data)
{
struct usbnet *dev = netdev_priv(netdev);
ee->magic = LAN95XX_EEPROM_MAGIC;
return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
}
static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
struct ethtool_eeprom *ee, u8 *data)
{
struct usbnet *dev = netdev_priv(netdev);
if (ee->magic != LAN95XX_EEPROM_MAGIC) {
netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
ee->magic);
return -EINVAL;
}
return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
}
static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
{
/* all smsc95xx registers */
return COE_CR - ID_REV + sizeof(u32);
}
static void
smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
void *buf)
{
struct usbnet *dev = netdev_priv(netdev);
unsigned int i, j;
int retval;
u32 *data = buf;
retval = smsc95xx_read_reg(dev, ID_REV, ®s->version);
if (retval < 0) {
netdev_warn(netdev, "REGS: cannot read ID_REV\n");
return;
}
for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
retval = smsc95xx_read_reg(dev, i, &data[j]);
if (retval < 0) {
netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
return;
}
}
}
static void smsc95xx_ethtool_get_wol(struct net_device *net,
struct ethtool_wolinfo *wolinfo)
{
struct usbnet *dev = netdev_priv(net);
struct smsc95xx_priv *pdata = dev->driver_priv;
wolinfo->supported = SUPPORTED_WAKE;
wolinfo->wolopts = pdata->wolopts;
}
static int smsc95xx_ethtool_set_wol(struct net_device *net,
struct ethtool_wolinfo *wolinfo)
{
struct usbnet *dev = netdev_priv(net);
struct smsc95xx_priv *pdata = dev->driver_priv;
int ret;
if (wolinfo->wolopts & ~SUPPORTED_WAKE)
return -EINVAL;
pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
if (ret < 0)
netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
return ret;
}
static u32 smsc95xx_get_link(struct net_device *net)
{
phy_read_status(net->phydev);
return net->phydev->link;
}
static void smsc95xx_ethtool_get_strings(struct net_device *netdev, u32 sset,
u8 *data)
{
switch (sset) {
case ETH_SS_TEST:
net_selftest_get_strings(data);
break;
}
}
static int smsc95xx_ethtool_get_sset_count(struct net_device *ndev, int sset)
{
switch (sset) {
case ETH_SS_TEST:
return net_selftest_get_count();
default:
return -EOPNOTSUPP;
}
}
static const struct ethtool_ops smsc95xx_ethtool_ops = {
.get_link = smsc95xx_get_link,
.nway_reset = phy_ethtool_nway_reset,
.get_drvinfo = usbnet_get_drvinfo,
.get_msglevel = usbnet_get_msglevel,
.set_msglevel = usbnet_set_msglevel,
.get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
.get_eeprom = smsc95xx_ethtool_get_eeprom,
.set_eeprom = smsc95xx_ethtool_set_eeprom,
.get_regs_len = smsc95xx_ethtool_getregslen,
.get_regs = smsc95xx_ethtool_getregs,
.get_wol = smsc95xx_ethtool_get_wol,
.set_wol = smsc95xx_ethtool_set_wol,
.get_link_ksettings = phy_ethtool_get_link_ksettings,
.set_link_ksettings = phy_ethtool_set_link_ksettings,
.get_ts_info = ethtool_op_get_ts_info,
.self_test = net_selftest,
.get_strings = smsc95xx_ethtool_get_strings,
.get_sset_count = smsc95xx_ethtool_get_sset_count,
};
static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
{
if (!netif_running(netdev))
return -EINVAL;
return phy_mii_ioctl(netdev->phydev, rq, cmd);
}
static void smsc95xx_init_mac_address(struct usbnet *dev)
{
u8 addr[ETH_ALEN];
/* maybe the boot loader passed the MAC address in devicetree */
if (!platform_get_ethdev_address(&dev->udev->dev, dev->net)) {
if (is_valid_ether_addr(dev->net->dev_addr)) {
/* device tree values are valid so use them */
netif_dbg(dev, ifup, dev->net, "MAC address read from the device tree\n");
return;
}
}
/* try reading mac address from EEPROM */
if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, addr) == 0) {
eth_hw_addr_set(dev->net, addr);
if (is_valid_ether_addr(dev->net->dev_addr)) {
/* eeprom values are valid so use them */
netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
return;
}
}
/* no useful static MAC address found. generate a random one */
eth_hw_addr_random(dev->net);
netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
}
static int smsc95xx_set_mac_address(struct usbnet *dev)
{
u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
int ret;
ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
if (ret < 0)
return ret;
return smsc95xx_write_reg(dev, ADDRH, addr_hi);
}
/* starts the TX path */
static int smsc95xx_start_tx_path(struct usbnet *dev)
{
struct smsc95xx_priv *pdata = dev->driver_priv;
unsigned long flags;
int ret;
/* Enable Tx at MAC */
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
pdata->mac_cr |= MAC_CR_TXEN_;
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
if (ret < 0)
return ret;
/* Enable Tx at SCSRs */
return smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
}
/* Starts the Receive path */
static int smsc95xx_start_rx_path(struct usbnet *dev)
{
struct smsc95xx_priv *pdata = dev->driver_priv;
unsigned long flags;
spin_lock_irqsave(&pdata->mac_cr_lock, flags);
pdata->mac_cr |= MAC_CR_RXEN_;
spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
return smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
}
static int smsc95xx_reset(struct usbnet *dev)
{
struct smsc95xx_priv *pdata = dev->driver_priv;
u32 read_buf, burst_cap;
int ret = 0, timeout;
netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
if (ret < 0)
return ret;
timeout = 0;
do {
msleep(10);
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
if (ret < 0)
return ret;
timeout++;
} while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
if (timeout >= 100) {
netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
return -ETIMEDOUT;
}
ret = smsc95xx_set_mac_address(dev);
if (ret < 0)
return ret;
netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
dev->net->dev_addr);
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
if (ret < 0)
return ret;
netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
read_buf);
read_buf |= HW_CFG_BIR_;
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
if (ret < 0)
return ret;
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
if (ret < 0)
return ret;
netif_dbg(dev, ifup, dev->net,
"Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
read_buf);
if (!turbo_mode) {
burst_cap = 0;
dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
} else if (dev->udev->speed == USB_SPEED_HIGH) {
burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
} else {
burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
}
netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
(ulong)dev->rx_urb_size);
ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
if (ret < 0)
return ret;
ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
if (ret < 0)
return ret;
netif_dbg(dev, ifup, dev->net,
"Read Value from BURST_CAP after writing: 0x%08x\n",
read_buf);
ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
if (ret < 0)
return ret;
ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
if (ret < 0)
return ret;
netif_dbg(dev, ifup, dev->net,
"Read Value from BULK_IN_DLY after writing: 0x%08x\n",
read_buf);
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
if (ret < 0)
return ret;
netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG: 0x%08x\n",
read_buf);
if (turbo_mode)
read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
read_buf &= ~HW_CFG_RXDOFF_;
/* set Rx data offset=2, Make IP header aligns on word boundary. */
read_buf |= NET_IP_ALIGN << 9;
ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
if (ret < 0)
return ret;
ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
if (ret < 0)
return ret;
netif_dbg(dev, ifup, dev->net,
"Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
if (ret < 0)
return ret;