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Merge pull request #2695 from mpilquist/topic/fix-warnings
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Fix compilation warnings
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mpilquist authored Oct 30, 2021
2 parents abf6bb0 + 50706c3 commit ae5aa01
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Showing 10 changed files with 19 additions and 20 deletions.
8 changes: 4 additions & 4 deletions core/shared/src/main/scala/fs2/Pull.scala
Original file line number Diff line number Diff line change
Expand Up @@ -858,7 +858,7 @@ object Pull extends PullLowPriority {
// Inner scope is getting closed b/c a parent was interrupted
val cl: Pull[G, X, Unit] = CanceledScope(cs.scopeId, interruption)
transformWith(cl)(getCont[Unit, G, X])
case action: Action[G, X, y] =>
case _: Action[G, X, y] =>
// all other actions, roll the interruption forwards
getCont[Unit, G, X](interruption)
case interrupted: Interrupted => interrupted // impossible
Expand Down Expand Up @@ -1164,7 +1164,7 @@ object Pull extends PullLowPriority {
}

viewL(stream) match {
case tst: Translate[h, G, _] => // y = Unit
case tst: Translate[h, G, _] @nowarn => // y = Unit
val translateRunner: Run[h, X, F[End]] = new TranslateRunner(tst.fk, getCont[Unit, G, X])
val composed: h ~> F = translation.compose[h](tst.fk)
go[h, X, End](scope, extendedTopLevelScope, composed, translateRunner, tst.stream)
Expand All @@ -1179,14 +1179,14 @@ object Pull extends PullLowPriority {
val fmrunr = new FlatMapR(getCont[Unit, G, X], fmout.fun)
F.unit >> go(scope, extendedTopLevelScope, translation, fmrunr, fmout.stream)

case u: Uncons[G, y] =>
case u: Uncons[G, y] @nowarn =>
val v = getCont[Option[(Chunk[y], Pull[G, y, Unit])], G, X]
// a Uncons is run on the same scope, without shifting.
val runr = new BuildR[G, y, End]
F.unit >> go(scope, extendedTopLevelScope, translation, runr, u.stream).attempt
.flatMap(_.fold(goErr(_, v), _.apply(new UnconsRunR(v))))

case s: StepLeg[G, y] =>
case s: StepLeg[G, y] @nowarn =>
val v = getCont[Option[Stream.StepLeg[G, y]], G, X]
val runr = new BuildR[G, y, End]
scope
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Original file line number Diff line number Diff line change
Expand Up @@ -244,7 +244,7 @@ object Demultiplexer {
payloadUnitStartAfterData: Boolean
): StepResult[Out] =
decodeHeader(acc, startedAtOffsetZero) match {
case Attempt.Failure(e: Err.InsufficientBits) =>
case Attempt.Failure(_: Err.InsufficientBits) =>
StepResult.state(DecodeState.AwaitingHeader(acc, startedAtOffsetZero))
case Attempt.Failure(_: ResetDecodeState) =>
StepResult.noOutput(None)
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Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ sealed abstract class GroupedSections[+A <: Section] {
object GroupedSections {
implicit class InvariantOps[A <: Section](val self: GroupedSections[A]) extends AnyVal {
def narrow[B <: A: ClassTag]: Option[GroupedSections[B]] = {
val matched = self.list.foldLeft(true) { (acc, s) =>
val matched = self.list.foldLeft(true) { (_, s) =>
s match { case _: B => true; case _ => false }
}
if (matched) Some(self.asInstanceOf[GroupedSections[B]])
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -165,7 +165,7 @@ object SectionCodec {
}

private def unknownSectionCase(tableId: Int): Case[BitVector, UnknownSection] = Case(
(hdr, verifyCrc) => bits,
(_, _) => bits,
(privateBits, ext, bits) =>
Attempt.successful(ext match {
case Some(e) => UnknownExtendedSection(tableId, privateBits, e, bits.bytes)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -50,18 +50,18 @@ object SectionFragmentCodec {
s => { val (ext, r) = fromSection(s); (PsiPrivateBits, ext, r) }
)

def extended[A, R: Codec](
def extended[A, R](
tableId: Int,
toSection: (BitVector, SectionExtension, R) => A,
fromSection: A => (BitVector, SectionExtension, R)
): SectionFragmentCodec[A] = {
)(implicit codecR: Codec[R]): SectionFragmentCodec[A] = {
val tid = tableId
val build = toSection
val extract = fromSection
new SectionFragmentCodec[A] {
type Repr = R
def tableId = tid
def subCodec(header: SectionHeader, verifyCrc: Boolean) = Codec[Repr]
def subCodec(header: SectionHeader, verifyCrc: Boolean) = codecR
def toSection(privateBits: BitVector, extension: Option[SectionExtension], data: Repr) =
Attempt.fromOption(
extension.map(ext => build(privateBits, ext, data)),
Expand Down Expand Up @@ -125,7 +125,7 @@ object SectionFragmentCodec {
SectionFragmentCodec.nonExtended[A, A](
tableId,
sHdr => toCodec(sHdr),
(bits, a) => a,
(_, a) => a,
a => (BitVector.empty, a)
)

Expand All @@ -136,7 +136,7 @@ object SectionFragmentCodec {
SectionFragmentCodec.nonExtendedWithCrc[A, A](
tableId,
(sHdr, verifyCrc) => toCodec(sHdr, verifyCrc),
(bits, a) => a,
(_, a) => a,
a => (BitVector.empty, a)
)
}
Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ object TransportStreamIndex {

def withPat(pat: ProgramAssociationTable): TransportStreamIndex = {
val programs = pat.programByPid.keys.toSet
copy(pat = Some(pat), pmts = pmts.view.filter { case (k, v) => programs(k) }.toMap)
copy(pat = Some(pat), pmts = pmts.view.filter { case (k, _) => programs(k) }.toMap)
}

def withPmt(pmt: ProgramMapTable): TransportStreamIndex =
Expand All @@ -100,7 +100,7 @@ object TransportStreamIndex {
Some(tsi.withPmt(pmt))
case cat: ConditionalAccessTable =>
Some(tsi.withCat(cat))
case other => None
case _ => None
}
val out = updatedTsi match {
case Some(newTsi) if newTsi != tsi =>
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ package fs2
package protocols

import cats.effect.{IO, IOApp}
import com.comcast.ip4s.{Ipv4Address, Port, SocketAddress}
import com.comcast.ip4s.{Ipv4Address, SocketAddress}
import fs2.interop.scodec.StreamDecoder
import fs2.io.file.{Files, Path}
import fs2.timeseries.TimeStamped
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,6 @@ object DescriptorTestData {
lazy val genIso639LanguageDescriptor: Gen[Iso639LanguageDescriptor] = for {
numberOfLanguagueField <- Gen.chooseNum(0, 63)
languageFields <- Gen.listOfN(numberOfLanguagueField, genLanguageField)
length = languageFields.size * 4
} yield Iso639LanguageDescriptor(languageFields.toVector)

lazy val genSystemClockDescriptor: Gen[SystemClockDescriptor] = for {
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ class PacketTest extends Fs2Suite {
val data = sections.foldLeft(BitVector.empty)(_ ++ _)
val packets = Packet.packetizeMany(Pid(0), ContinuityCounter(0), sections)

packets.zipWithIndex.foreach { case (packet, idx) =>
packets.zipWithIndex.foreach { case (_, idx) =>
val payloadOffset = if (idx == 0) 0 else 10 * ((idx * 183) / 10 + 1) - (idx * 183)
val offset = 183L * 8 * idx
assertEquals(
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -118,8 +118,8 @@ class SectionCodecTest extends Fs2Suite {
implicit val sfc: SectionFragmentCodec[SmallSection] =
SectionFragmentCodec.nonExtended[SmallSection, Int](
0,
h => (constant(bin"0") ~> uint(7)),
(p, i) => SmallSection(i),
_ => (constant(bin"0") ~> uint(7)),
(_, i) => SmallSection(i),
ss => (bin"010", ss.x)
)
val sc = SectionCodec.supporting[SmallSection]
Expand All @@ -129,7 +129,7 @@ class SectionCodecTest extends Fs2Suite {
val ss1 = encodedSections(1).bytes
val indexOfInt = ss0.toIndexedSeq.zipWithIndex
.find { case (x, idx) => ss1(idx.toLong) != x }
.map { case (x, idx) => idx }
.map { case (_, idx) => idx }
.get
val ss255 = ss0.update(indexOfInt.toLong, 255.toByte)

Expand Down

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