Merge pull request #2001 from ucb-bar/b_ext

.github/scripts/defaults.sh

@@ -50,7 +50,7 @@ mapping["chipyard-boomv3"]=" CONFIG=MediumBoomV3CosimConfig"
 mapping["chipyard-dmiboomv3"]=" CONFIG=dmiCheckpointingMediumBoomV3Config"
 mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
 mapping["chipyard-dmiboomv4"]=" CONFIG=dmiCheckpointingMediumBoomV4Config"
-mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
+mapping["chipyard-spike"]=" CONFIG=SpikeZicntrConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
 mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"

.github/scripts/run-tests.sh

@@ -13,16 +13,11 @@ DISABLE_SIM_PREREQ="BREAK_SIM_PREREQ=1"
 MAPPING_FLAGS=${mapping[$1]}
 
 run_bmark () {
-    make run-bmark-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
+    make run-bmark-tests-fast -j1 -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }
 
 run_asm () {
-    make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
-}
-
-run_both () {
-    run_bmark $@
-    run_asm $@
+    make run-asm-tests-fast -j1 -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }
 
 run_tracegen () {
@@ -35,7 +30,8 @@ run_binary () {
 
 case $1 in
     chipyard-rocket)
-        run_bmark
+        run_bmark LOADMEM=1
+        run_asm LOADMEM=1
         make -C $LOCAL_CHIPYARD_DIR/tests
         # Test run-binary with and without loadmem
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
@@ -49,37 +45,21 @@ case $1 in
         # Test cospike without checkpoint-restore
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1
         ;;
-    chipyard-boomv3)
-        run_bmark
-        ;;
-    chipyard-boomv4)
-        run_bmark
-        ;;
-    chipyard-shuttle)
-        run_bmark ${mapping[$1]}
-        ;;
-    chipyard-dmiboomv3)
-        # Test checkpoint-restore
-        $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
-        run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.unused.10000.defaultspikedts.loadarch
+    chipyard-boomv3|chipyard-boomv4|chipyard-shuttle|chipyard-spike)
+        run_asm LOADMEM=1
+        run_bmark LOADMEM=1
         ;;
-    chipyard-dmiboomv4)
+    chipyard-dmiboomv3|chipyard-dmiboomv4)
         # Test checkpoint-restore
         $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
         run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.unused.10000.defaultspikedts.loadarch
         ;;
-    chipyard-spike)
-        run_bmark
-        ;;
     chipyard-hetero)
-        run_bmark
+        run_bmark LOADMEM=1
         ;;
     chipyard-prefetchers)
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1
         ;;
-    rocketchip)
-        run_bmark
-        ;;
     chipyard-gemmini)
         GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
         rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests
@@ -100,17 +80,17 @@ case $1 in
 	make -C $LOCAL_CHIPYARD_DIR/tests
 
 	# test streaming-passthrough
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv LOADMEM=1
 
 	# test streaming-fir
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv LOADMEM=1
 
 	# test fft
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv LOADMEM=1
 	;;
     chipyard-nvdla)
 	make -C $LOCAL_CHIPYARD_DIR/tests
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv LOADMEM=1
 	;;
     chipyard-manyperipherals)
 	# SPI Flash read tests
@@ -119,7 +99,7 @@ case $1 in
         ;;
     chipyard-spiflashwrite)
         make -C $LOCAL_CHIPYARD_DIR/tests
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv LOADMEM=1
         [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img  | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false
         ;;
     chipyard-tethered)

common.mk

@@ -377,10 +377,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% | $(output
 	ln -sf $< $@
 
 $(output_dir)/%.run: $(output_dir)/% $(SIM_PREREQ)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$<) $(PERMISSIVE_OFF)  $< </dev/null | tee $<.log) && touch $@
 
 $(output_dir)/%.out: $(output_dir)/% $(SIM_PREREQ)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$<) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
 
 #########################################################################################
 # include build/project specific makefrags made from the generator

generators/chipyard/src/main/scala/SpikeTile.scala

@@ -17,7 +17,8 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
 case class SpikeCoreParams(
-  nPMPs: Int = 16
+  nPMPs: Int = 16,
+  useZicntr: Boolean = false
 ) extends CoreParams {
   val xLen = 64
   val pgLevels = 5
@@ -61,11 +62,10 @@ case class SpikeCoreParams(
   val btbEntries = 0
   val bhtEntries = 0
   val traceHasWdata = false
-  val useBitManip = false
-  val useBitManipCrypto = false
-  val useCryptoNIST = false
-  val useCryptoSM = false
   val useConditionalZero = false
+  val useZba = true
+  val useZbb = true
+  val useZbs = true
 
   override def vLen = 128
   override def eLen = 64
@@ -121,7 +121,17 @@ class SpikeTile(
   val slaveNode = TLIdentityNode()
 
   // Note: Rocket doesn't support zicntr but Spike does (err on the side of having Rocket's ISA)
-  override def isaDTS = "rv64imafdcv_zicsr_zifencei_zihpm_zvl128b_zve64d"
+  override def isaDTS = (Seq(
+    "rv64imafdcbv",
+    "zicsr",
+    "zifencei",
+    "zihpm",
+    "zvl128b",
+    "zve64d",
+    "zba",
+    "zbb",
+    "zbs"
+  ) ++ spikeTileParams.core.useZicntr.option("zicntr")).mkString("_")
 
   // Required entry of CPU device in the device tree for interrupt purpose
   val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("ucb-bar,spike", "riscv")) {
@@ -474,6 +484,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   }
 }
 
+class WithSpikeZicntr extends TileAttachConfig[SpikeTileAttachParams](t =>
+  t.copy(tileParams=t.tileParams.copy(core=t.tileParams.core.copy(useZicntr=true)))
+)
+
 class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams()
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {

generators/chipyard/src/main/scala/TestSuites.scala

@@ -95,6 +95,9 @@ class TestSuiteHelper
       val (rvi, rvu) =
         if (xlen == 64) ((if (vm) rv64i else rv64pi), (if (coreParams.mulDiv.isDefined) rv64u else List(rv64ui)))
         else            ((if (vm) rv32i else rv32pi), (if (coreParams.mulDiv.isDefined) rv32u else List(rv32ui)))
+      if (coreParams.useZba) addSuites(env.map(if (xlen == 64) rv64uzba else rv32uzba))
+      if (coreParams.useZbb) addSuites(env.map(if (xlen == 64) rv64uzbb else rv32uzbb))
+      if (coreParams.useZbs) addSuites(env.map(if (xlen == 64) rv64uzbs else rv32uzbs))
 
       addSuites(rvi.map(_("p")))
       addSuites(rvu.map(_("p")))

generators/chipyard/src/main/scala/config/AraConfigs.scala

@@ -6,14 +6,14 @@ import saturn.common.{VectorParams}
 // Rocket-integrated configs
 class V4096Ara2LaneRocketConfig extends Config(
   new ara.WithAraRocketVectorUnit(4096, 2) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 
 class V8192Ara4LaneRocketConfig extends Config(
   new ara.WithAraRocketVectorUnit(8192, 4) ++
   new chipyard.config.WithSystemBusWidth(128) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -17,7 +17,7 @@ class ChipLikeRocketConfig extends Config(
   // Set up tiles
   //==================================
   new freechips.rocketchip.rocket.WithAsynchronousCDCs(depth=8, sync=3) ++ // Add async crossings between RocketTile and uncore
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++                      // 1 RocketTile
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++                      // 1 RocketTile
 
   //==================================
   // Set up I/O

generators/chipyard/src/main/scala/config/ChipletConfigs.scala

@@ -35,7 +35,7 @@ class SymmetricChipletRocketConfig extends Config(
     replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
   ) ++
   new testchipip.soc.WithOffchipBus ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
@@ -71,7 +71,7 @@ class RocketCoreChipletConfig extends Config(
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // LLC-only chiplet

generators/chipyard/src/main/scala/config/ClockingConfigs.scala

@@ -14,7 +14,7 @@ import testchipip.soc.{OBUS}
 // Note: This is what designs inheriting from AbstractConfig do by default
 class DefaultClockingRocketConfig extends Config(
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This is a more physically realistic approach, normally we can't punch out a separate
@@ -23,12 +23,12 @@ class DefaultClockingRocketConfig extends Config(
 // clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info
 class ChipLikeClockingRocketConfig extends Config(
   new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single
 // clock input pin.
 class SingleClockBroadcastRocketConfig extends Config(
   new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -8,27 +8,27 @@ import org.chipsalliance.cde.config.{Config}
 
 class LargeBoomAndRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(1) ++                    // single-core boom
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++         // single rocket-core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class DualLargeBoomAndDualRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
-  new freechips.rocketchip.rocket.WithNBigCores(2) ++  // add 2 rocket cores
+  new freechips.rocketchip.rocket.WithNHugeCores(2) ++  // add 2 rocket cores
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DualBoomAndSingleRocket
 class DualLargeBoomAndSingleRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++  // add 1 rocket core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++  // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DualBoomAndSingleRocket
 
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
   new freechips.rocketchip.rocket.WithNSmallCores(1) ++    // Add a small "control" core
   new boom.v3.common.WithNLargeBooms(1) ++                 // Add 1 boom core
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++      // add 1 rocket core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++      // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala

@@ -10,51 +10,51 @@ import org.chipsalliance.cde.config.{Config}
 class FFTRocketConfig extends Config(
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++              // TODO: hack around dontTouch not working in SFC
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: FFTRocketConfig
 
 // DOC include start: GCDTLRocketConfig
 class GCDTLRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDTLRocketConfig
 
 // DOC include start: GCDAXI4BlackBoxRocketConfig
 class GCDAXI4BlackBoxRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++            // Use GCD blackboxed verilog, connect by AXI4->Tilelink
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDAXI4BlackBoxRocketConfig
 
 // DOC include start: InitZeroRocketConfig
 class InitZeroRocketConfig extends Config(
   new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++   // add InitZero
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: InitZeroRocketConfig
 
 class StreamingPassthroughRocketConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: StreamingFIRRocketConfig
 class StreamingFIRRocketConfig extends Config (
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: StreamingFIRRocketConfig
 
 class SmallNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("small") ++               // add a small NVDLA
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class LargeNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("large", true) ++         // add a large NVDLA with synth. rams
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class ManyMMIOAcceleratorRocketConfig extends Config(
@@ -63,5 +63,5 @@ class ManyMMIOAcceleratorRocketConfig extends Config(
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)