Merge pull request #2013 from ucb-bar/split-v1-w-firrtl2

Support FIRRTL2 bridge + Chisel 6 annos for FireSim

.github/scripts/check-commit.sh

@@ -83,7 +83,7 @@ dir="software"
 branches=("master" "dev")
 search
 
-submodules=("DRAMSim2" "axe" "dsptools" "dsptools-chisel3" "rocket-dsp-utils" "torture" "fixedpoint" "fixedpoint-chisel3" "cde" "midas-targetutils")
+submodules=("DRAMSim2" "axe" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde" "firrtl2")
 dir="tools"
 branches=("master" "dev" "main")
 search

.gitmodules

@@ -115,12 +115,6 @@
 [submodule "tools/circt"]
 	path = tools/circt
 	url = https://github.com/llvm/circt.git
-[submodule "tools/dsptools-fixedpoint"]
-	path = tools/dsptools-chisel3
-	url = https://github.com/ucb-bar/dsptools.git
-[submodule "tools/fixedpoint-chisel3"]
-	path = tools/fixedpoint-chisel3
-	url = https://github.com/ucb-bar/fixedpoint.git
 [submodule "tools/install-circt"]
 	path = tools/install-circt
 	url = https://github.com/circt/install-circt.git
@@ -139,9 +133,6 @@
 [submodule "tools/fixedpoint"]
 	path = tools/fixedpoint
 	url = https://github.com/ucb-bar/fixedpoint.git
-[submodule "tools/midas-targetutils"]
-	path = tools/midas-targetutils
-	url = https://github.com/firesim/midas-targetutils.git
 [submodule "generators/rerocc"]
 	path = generators/rerocc
 	url = https://github.com/ucb-bar/rerocc.git
@@ -157,3 +148,6 @@
 [submodule "generators/ara"]
 	path = generators/ara
 	url = https://github.com/ucb-bar/ara-wrapper.git
+[submodule "tools/firrtl2"]
+	path = tools/firrtl2
+	url = https://github.com/ucb-bar/firrtl2.git

build.sbt

@@ -1,10 +1,10 @@
 import Tests._
 
-val chisel6 = sys.env.get("USE_CHISEL6").isDefined
 val chisel6Version = "6.5.0"
+val chiselTestVersion = "6.0.0"
+val scalaVersionFromChisel = "2.13.12"
+
 val chisel3Version = "3.6.1"
-val chiselTestVersion = if (chisel6) "6.0.0" else "0.6.0"
-val scalaVersionFromChisel = if (chisel6) "2.13.12" else "2.13.10"
 
 // This gives us a nicer handle to the root project instead of using the
 // implicit one
@@ -97,7 +97,7 @@ lazy val chisel3Settings = Seq(
   addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chisel3Version cross CrossVersion.full)
 )
 
-lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq(
+lazy val chiselSettings = chisel6Settings ++ Seq(
   libraryDependencies ++= Seq(
     "org.apache.commons" % "commons-lang3" % "3.12.0",
     "org.apache.commons" % "commons-text" % "1.9"
@@ -118,7 +118,7 @@ lazy val scalaTestSettings =  Seq(
 lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
   .settings(chiselSettings)
   .settings(commonSettings)
-  .dependsOn(if (chisel6) midas_standalone_target_utils else midas_target_utils)
+  .dependsOn(midas_target_utils)
   .settings(scalaTestSettings)
 
 lazy val rocketMacros  = (project in rocketChipDir / "macros")
@@ -153,21 +153,20 @@ lazy val testchipip = (project in file("generators/testchipip"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-val stageDir = if (chisel6) "tools/stage/src/main/scala" else "tools/stage-chisel3/src/main/scala"
 lazy val chipyard = (project in file("generators/chipyard"))
   .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
-    compressacc, saturn, ara)
+    compressacc, saturn, ara, firrtl2_bridge)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(
     libraryDependencies ++= Seq(
       "org.reflections" % "reflections" % "0.10.2"
     )
   )
   .settings(commonSettings)
-  .settings(Compile / unmanagedSourceDirectories += file(stageDir))
+  .settings(Compile / unmanagedSourceDirectories += file("tools/stage/src/main/scala"))
 
 lazy val compressacc = (project in file("generators/compress-acc"))
   .dependsOn(rocketchip)
@@ -270,13 +269,11 @@ lazy val tapeout = (project in file("./tools/tapeout/"))
   .settings(scalaVersion := "2.13.10") // stuck on chisel3 2.13.10
   .settings(libraryDependencies ++= Seq("com.typesafe.play" %% "play-json" % "2.9.2"))
 
-val fixedpointDir = if (chisel6) "./tools/fixedpoint" else "./tools/fixedpoint-chisel3"
-lazy val fixedpoint = freshProject("fixedpoint", file(fixedpointDir))
+lazy val fixedpoint = freshProject("fixedpoint", file("./tools/fixedpoint"))
   .settings(chiselSettings)
   .settings(commonSettings)
 
-val dsptoolsDir = if (chisel6) "./tools/dsptools" else "./tools/dsptools-chisel3"
-lazy val dsptools = freshProject("dsptools", file(dsptoolsDir))
+lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
   .dependsOn(fixedpoint)
   .settings(
     chiselSettings,
@@ -322,30 +319,58 @@ lazy val chipyard_fpga = (project in file("./fpga"))
 
 // Components of FireSim
 
+lazy val firrtl2 = freshProject("firrtl2", file("./tools/firrtl2"))
+  .enablePlugins(BuildInfoPlugin)
+  .enablePlugins(Antlr4Plugin)
+  .settings(commonSettings)
+  .settings(
+    sourceDirectory := file("./tools/firrtl2/src"),
+    scalacOptions ++= Seq(
+      "-language:reflectiveCalls",
+      "-language:existentials",
+      "-language:implicitConversions"),
+    libraryDependencies ++= Seq(
+      "org.scalatest" %% "scalatest" % "3.2.14" % "test",
+      "org.scalatestplus" %% "scalacheck-1-15" % "3.2.11.0" % "test",
+      "com.github.scopt" %% "scopt" % "4.1.0",
+      "org.json4s" %% "json4s-native" % "4.1.0-M4",
+      "org.apache.commons" % "commons-text" % "1.10.0",
+      "com.lihaoyi" %% "os-lib" % "0.8.1",
+      "org.scala-lang.modules" %% "scala-parallel-collections" % "1.0.4"),
+    Antlr4 / antlr4GenVisitor := true,
+    Antlr4 / antlr4GenListener := true,
+    Antlr4 / antlr4PackageName := Option("firrtl2.antlr"),
+    Antlr4 / antlr4Version := "4.9.3",
+    Antlr4 / javaSource := (Compile / sourceManaged).value,
+    buildInfoPackage := "firrtl2",
+    buildInfoUsePackageAsPath := true,
+    buildInfoKeys := Seq[BuildInfoKey](buildInfoPackage, version, scalaVersion, sbtVersion)
+  )
+
+lazy val firrtl2_bridge = freshProject("firrtl2_bridge", file("./tools/firrtl2/bridge"))
+  .dependsOn(firrtl2)
+  .settings(commonSettings)
+  .settings(chiselSettings)
+
 lazy val firesimAsLibrary = sys.env.get("FIRESIM_STANDALONE") == None
 lazy val firesimDir = if(firesimAsLibrary) {
   file("sims/firesim")
 } else {
   file("sims/firesim-staging/firesim-symlink")
 }
 
-// TODO: AJG: Fix
 // Contains annotations & firrtl passes you may wish to use in rocket-chip without
-// introducing a circular dependency between RC and MIDAS
-// this should be minimally dependent on firesim
+// introducing a circular dependency between RC and MIDAS.
+// Minimal in scope (should only depend on Chisel/Firrtl that is
+// cross-compilable between FireSim Chisel 3.* and Chipyard Chisel 6+)
 lazy val midas_target_utils = (project in firesimDir / "sim/midas/targetutils")
   .settings(commonSettings)
   .settings(chiselSettings)
 
-// compiles with chisel6 (only the APIs)
-lazy val midas_standalone_target_utils = (project in file("tools/midas-targetutils"))
-  .settings(commonSettings)
-  .settings(chiselSettings)
-// TODO: AJG: ^ Fix
-
 // Provides API for bridges to be created in the target.
 // Includes target-side of FireSim-provided bridges and their interfaces that are shared
-// between FireSim and the target. Minimal in scope (should only depend on Chisel/Firrtl2)
+// between FireSim and the target. Minimal in scope (should only depend on Chisel/Firrtl that is
+// cross-compilable between FireSim Chisel 3.* and Chipyard Chisel 6+)
 lazy val firesim_lib = (project in firesimDir / "sim/firesim-lib")
   .dependsOn(midas_target_utils)
   .settings(commonSettings)

common.mk

@@ -88,9 +88,9 @@ CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are init
 SCALA_EXT = scala
 VLOG_EXT = sv v
 FIRESIM_DIR = $(if $(FIRESIM_STANDALONE),sims/firesim-staging/firesim-symlink,sims/firesim)
-FIRESIM_SOURCE_DIRS = $(addprefix $(FIRESIM_DIR)/,sim/firesim-lib sim/midas/targetutils) $(addprefix generators/firechip/,core bridge-interfaces)
+FIRESIM_SOURCE_DIRS = $(addprefix $(FIRESIM_DIR)/,sim/firesim-lib sim/midas/targetutils) $(addprefix generators/firechip/,core bridge-interfaces) tools/firrtl2
 CHIPYARD_SOURCE_DIRS = \
-	$(filter-out $(base_dir)/generators/firechip,$(wildcard $(addprefix $(base_dir)/,generators/* fpga/fpga-shells fpga/src tools/stage tools/stage-chisel3))) \
+	$(filter-out $(base_dir)/generators/firechip,$(wildcard $(addprefix $(base_dir)/,generators/* fpga/fpga-shells fpga/src tools/stage))) \
 	$(addprefix $(base_dir)/,$(FIRESIM_SOURCE_DIRS))
 CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT))
 CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT))

generators/firechip/bridgestubs/src/main/makefrag/bridges/build.mk

@@ -21,8 +21,9 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: firesim_target_symlink_hook
 			CONFIG=$(TARGET_CONFIG) \
 			CONFIG_PACKAGE=$(TARGET_CONFIG_PACKAGE) \
 			GENERATOR_PACKAGE=chipyard \
+			EXTRA_CHISEL_OPTIONS=--emit-legacy-sfc \
 			TB=unused \
 			TOP=unused
 	# $(long_name) must be same as Chipyard
-	ln -sf $(CHIPYARD_STAGING_DIR)/generated-src/$(long_name)/$(long_name).fir $(FIRRTL_FILE)
+	ln -sf $(CHIPYARD_STAGING_DIR)/generated-src/$(long_name)/$(long_name).sfc.fir $(FIRRTL_FILE)
 	ln -sf $(CHIPYARD_STAGING_DIR)/generated-src/$(long_name)/$(long_name).anno.json $(ANNO_FILE)

generators/firechip/chip/src/main/makefrag/firesim/build.mk

@@ -21,10 +21,11 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: firesim_target_symlink_hook
 			CONFIG=$(TARGET_CONFIG) \
 			CONFIG_PACKAGE=$(TARGET_CONFIG_PACKAGE) \
 			GENERATOR_PACKAGE=chipyard \
+			EXTRA_CHISEL_OPTIONS=--emit-legacy-sfc \
 			TB=unused \
 			TOP=unused
 	# $(long_name) must be same as Chipyard
-	ln -sf $(CHIPYARD_STAGING_DIR)/generated-src/$(long_name)/$(long_name).fir $(FIRRTL_FILE)
+	ln -sf $(CHIPYARD_STAGING_DIR)/generated-src/$(long_name)/$(long_name).sfc.fir $(FIRRTL_FILE)
 	ln -sf $(CHIPYARD_STAGING_DIR)/generated-src/$(long_name)/$(long_name).anno.json $(ANNO_FILE)
 	# .d needed to run metasim CI tests
 	ln -sf $(CHIPYARD_STAGING_DIR)/generated-src/$(long_name)/$(long_name).d $(GENERATED_DIR)/$(long_name).d

generators/firechip/chip/src/main/scala/FireSim.scala

@@ -73,8 +73,8 @@ class FireSimClockBridgeInstantiator extends HarnessClockInstantiator {
 
 // for all cover statments in an RC-based design, emit an annotation
 class FireSimPropertyLibrary extends property.BasePropertyLibrary {
-  def generateProperty(prop_param: property.BasePropertyParameters)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo): Unit = {
-    if (!(prop_param.cond.isLit) && chisel3.experimental.DataMirror.internal.isSynthesizable(prop_param.cond)) {
+  def generateProperty(prop_param: property.BasePropertyParameters)(implicit sourceInfo: chisel3.experimental.SourceInfo): Unit = {
+    if (!(prop_param.cond.isLit) && chisel3.reflect.DataMirror.internal.isSynthesizable(prop_param.cond)) {
       annotate(new chisel3.experimental.ChiselAnnotation {
         val implicitClock = chisel3.Module.clock
         val implicitReset = chisel3.Module.reset

project/plugins.sbt

@@ -1,3 +1,6 @@
 addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "2.1.1")
 addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4")
 addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.6")
+addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "1.1.1")
+addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2")
+addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.11.0")

sims/firesim-staging/Makefile

@@ -14,7 +14,7 @@ sim_dir=$(abspath .)
 include $(base_dir)/variables.mk
 
 #########################################################################################
-# generate firrtl + annos needed for firesim
+# generate firrtl + annos needed for firesim (should also produce a *.sfc.fir file)
 #########################################################################################
 .PHONY: default
 default: firrtl