From efcc8a3fe74bd851c088cd66a498134595002afc Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 15:54:22 -0700
Subject: [PATCH 1/9] Enable B-ext testsuites

---
 generators/chipyard/src/main/scala/TestSuites.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
index 11e86e06e2..39e58a0a5c 100644
--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -95,6 +95,9 @@ class TestSuiteHelper
       val (rvi, rvu) =
         if (xlen == 64) ((if (vm) rv64i else rv64pi), (if (coreParams.mulDiv.isDefined) rv64u else List(rv64ui)))
         else            ((if (vm) rv32i else rv32pi), (if (coreParams.mulDiv.isDefined) rv32u else List(rv32ui)))
+      if (coreParams.useZba) addSuites(env.map(if (xlen == 64) rv64uzba else rv32uzba))
+      if (coreParams.useZbb) addSuites(env.map(if (xlen == 64) rv64uzbb else rv32uzbb))
+      if (coreParams.useZbs) addSuites(env.map(if (xlen == 64) rv64uzbs else rv32uzbs))
 
       addSuites(rvi.map(_("p")))
       addSuites(rvu.map(_("p")))

From 01b4871ee557f94d9a2760d4e65fc3c8591ca216 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 16:23:53 -0700
Subject: [PATCH 2/9] Make run-asm-tests work with LOADMEM

---
 common.mk                                          | 4 ++--
 generators/chipyard/src/main/scala/SpikeTile.scala | 7 ++++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/common.mk b/common.mk
index 7c3d159ae2..90aa049da4 100644
--- a/common.mk
+++ b/common.mk
@@ -377,10 +377,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% | $(output
 	ln -sf $< $@
 
 $(output_dir)/%.run: $(output_dir)/% $(SIM_PREREQ)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$<) $(PERMISSIVE_OFF)  $< </dev/null | tee $<.log) && touch $@
 
 $(output_dir)/%.out: $(output_dir)/% $(SIM_PREREQ)
-	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
+	(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$<) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
 
 #########################################################################################
 # include build/project specific makefrags made from the generator
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index 7913849b35..d30b4a8720 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -61,11 +61,12 @@ case class SpikeCoreParams(
   val btbEntries = 0
   val bhtEntries = 0
   val traceHasWdata = false
-  val useBitManip = false
-  val useBitManipCrypto = false
   val useCryptoNIST = false
   val useCryptoSM = false
   val useConditionalZero = false
+  val useZba = true
+  val useZbb = true
+  val useZbs = true
 
   override def vLen = 128
   override def eLen = 64
@@ -121,7 +122,7 @@ class SpikeTile(
   val slaveNode = TLIdentityNode()
 
   // Note: Rocket doesn't support zicntr but Spike does (err on the side of having Rocket's ISA)
-  override def isaDTS = "rv64imafdcv_zicsr_zifencei_zihpm_zvl128b_zve64d"
+  override def isaDTS = "rv64imafdcbv_zicsr_zifencei_zihpm_zvl128b_zve64d_zba_zbb_zbs"
 
   // Required entry of CPU device in the device tree for interrupt purpose
   val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("ucb-bar,spike", "riscv")) {

From fc84e6d0a7c1d64477043a409a80773f559be119 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 16:29:18 -0700
Subject: [PATCH 3/9] Run tests with LOADMEM in CI

---
 .github/scripts/run-tests.sh | 44 ++++++++++--------------------------
 1 file changed, 12 insertions(+), 32 deletions(-)

diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index f15b66663b..30ebb5d0e0 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -20,11 +20,6 @@ run_asm () {
     make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }
 
-run_both () {
-    run_bmark $@
-    run_asm $@
-}
-
 run_tracegen () {
     make tracegen -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }
@@ -35,7 +30,8 @@ run_binary () {
 
 case $1 in
     chipyard-rocket)
-        run_bmark
+        run_bmark LOADMEM=1
+        run_asm LOADMEM=1
         make -C $LOCAL_CHIPYARD_DIR/tests
         # Test run-binary with and without loadmem
         run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
@@ -49,37 +45,21 @@ case $1 in
         # Test cospike without checkpoint-restore
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1
         ;;
-    chipyard-boomv3)
-        run_bmark
-        ;;
-    chipyard-boomv4)
-        run_bmark
-        ;;
-    chipyard-shuttle)
-        run_bmark ${mapping[$1]}
-        ;;
-    chipyard-dmiboomv3)
-        # Test checkpoint-restore
-        $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
-        run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.unused.10000.defaultspikedts.loadarch
+    chipyard-boomv3|chipyard-boomv4|chipyard-shuttle|chipyard-spike)
+        run_asm LOADMEM=1
+        run_bmark LOADMEM=1
         ;;
-    chipyard-dmiboomv4)
+    chipyard-dmiboomv3|chipyard-dmiboomv4)
         # Test checkpoint-restore
         $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
         run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.unused.10000.defaultspikedts.loadarch
         ;;
-    chipyard-spike)
-        run_bmark
-        ;;
     chipyard-hetero)
-        run_bmark
+        run_bmark LOADMEM=1
         ;;
     chipyard-prefetchers)
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1
         ;;
-    rocketchip)
-        run_bmark
-        ;;
     chipyard-gemmini)
         GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
         rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests
@@ -100,17 +80,17 @@ case $1 in
 	make -C $LOCAL_CHIPYARD_DIR/tests
 
 	# test streaming-passthrough
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv LOADMEM=1
 
 	# test streaming-fir
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv LOADMEM=1
 
 	# test fft
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv LOADMEM=1
 	;;
     chipyard-nvdla)
 	make -C $LOCAL_CHIPYARD_DIR/tests
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv LOADMEM=1
 	;;
     chipyard-manyperipherals)
 	# SPI Flash read tests
@@ -119,7 +99,7 @@ case $1 in
         ;;
     chipyard-spiflashwrite)
         make -C $LOCAL_CHIPYARD_DIR/tests
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv LOADMEM=1
         [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img  | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false
         ;;
     chipyard-tethered)

From bf57ac92237d2d2b38c6a012d9ed2c278387c28a Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 16:37:50 -0700
Subject: [PATCH 4/9] Remove deprecated SpikeTile params

---
 generators/chipyard/src/main/scala/SpikeTile.scala | 2 --
 1 file changed, 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index d30b4a8720..b6f3627748 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -61,8 +61,6 @@ case class SpikeCoreParams(
   val btbEntries = 0
   val bhtEntries = 0
   val traceHasWdata = false
-  val useCryptoNIST = false
-  val useCryptoSM = false
   val useConditionalZero = false
   val useZba = true
   val useZbb = true

From 99fc90386863e10bef7d353e4c4f9b7bcd00ac46 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 16:58:47 -0700
Subject: [PATCH 5/9] Bump core submodules to support B extension

---
 generators/boom                                            | 2 +-
 .../chipyard/src/main/scala/example/TutorialTile.scala     | 7 +++----
 generators/cva6                                            | 2 +-
 generators/ibex                                            | 2 +-
 generators/rerocc                                          | 2 +-
 generators/riscv-sodor                                     | 2 +-
 generators/rocket-chip                                     | 2 +-
 generators/shuttle                                         | 2 +-
 8 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/generators/boom b/generators/boom
index 6b5523a4c3..64dae5bd32 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 6b5523a4c3cf1cfd8fedbe9be96a318bc1bf6c60
+Subproject commit 64dae5bd3248c3c49b805d2d08848838356fe373
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index bc2bb7084d..b4b0f03f36 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -64,12 +64,11 @@ case class MyCoreParams(
   val decodeWidth: Int = 1 // TODO: Check
   val fetchWidth: Int = 1 // TODO: Check
   val retireWidth: Int = 2
-  val useBitManip: Boolean = false
-  val useBitManipCrypto: Boolean = false
-  val useCryptoNIST: Boolean = false
-  val useCryptoSM: Boolean = false
   val traceHasWdata: Boolean = false
   val useConditionalZero = false
+  val useZba: Boolean = false
+  val useZbb: Boolean = false
+  val useZbs: Boolean = false
 }
 
 // DOC include start: CanAttachTile
diff --git a/generators/cva6 b/generators/cva6
index cafef4a4b8..a258461022 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit cafef4a4b8722e5a18bf3ddad359926fe92a0808
+Subproject commit a2584610225ab296c4fb77a66f70eec64908efd0
diff --git a/generators/ibex b/generators/ibex
index 06b3983d36..1a030b1d20 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 06b3983d36105c850d2feeaf104047bd9b5c4ac6
+Subproject commit 1a030b1d20e0bfb3f8ca250549f4826f1d2b2c32
diff --git a/generators/rerocc b/generators/rerocc
index 7281a84a6c..2c53d7e9fd 160000
--- a/generators/rerocc
+++ b/generators/rerocc
@@ -1 +1 @@
-Subproject commit 7281a84a6c1ac9165b886eb490a2e1cc97ee13c7
+Subproject commit 2c53d7e9fda1d6bd8f2b04dadb5bf1bfc699ae0b
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index 83c7e490b8..343e487d2a 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit 83c7e490b85216a3e74d31aa04c62b4f9e33ddc4
+Subproject commit 343e487d2ad58aef8c1c013f9687c65ebc805be1
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 3e2095460f..044a434049 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 3e2095460f8b78706e80fcfcc5b12bb10211e935
+Subproject commit 044a4340499f5fe4b104da0efa64d7a1f9d07812
diff --git a/generators/shuttle b/generators/shuttle
index 4d6f1dcddd..2ece93b0a1 160000
--- a/generators/shuttle
+++ b/generators/shuttle
@@ -1 +1 @@
-Subproject commit 4d6f1dcddd85894ba70e63f96fe0754505ee292e
+Subproject commit 2ece93b0a10187550d82d139bda1032e63e4507c

From 6875beff7f759363cf3473b3847a759a0ba3c009 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 16:59:07 -0700
Subject: [PATCH 6/9] Switch to B-enabled rocket configs globally

---
 .../src/main/scala/config/AraConfigs.scala    |  4 +--
 .../src/main/scala/config/ChipConfigs.scala   |  2 +-
 .../main/scala/config/ChipletConfigs.scala    |  4 +--
 .../main/scala/config/ClockingConfigs.scala   |  6 ++--
 .../src/main/scala/config/HeteroConfigs.scala |  8 ++---
 .../scala/config/MMIOAcceleratorConfigs.scala | 18 +++++------
 .../scala/config/MemorySystemConfigs.scala    | 14 ++++-----
 .../src/main/scala/config/NoCConfigs.scala    | 10 +++----
 .../config/PeripheralDeviceConfigs.scala      | 24 +++++++--------
 .../scala/config/RoCCAcceleratorConfigs.scala | 18 +++++------
 .../src/main/scala/config/RocketConfigs.scala | 30 +++++++++----------
 .../src/main/scala/config/SaturnConfigs.scala | 20 ++++++-------
 .../main/scala/config/TutorialConfigs.scala   |  6 ++--
 generators/saturn                             |  2 +-
 14 files changed, 83 insertions(+), 83 deletions(-)

diff --git a/generators/chipyard/src/main/scala/config/AraConfigs.scala b/generators/chipyard/src/main/scala/config/AraConfigs.scala
index 803ff6212e..a408aeea78 100644
--- a/generators/chipyard/src/main/scala/config/AraConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/AraConfigs.scala
@@ -6,14 +6,14 @@ import saturn.common.{VectorParams}
 // Rocket-integrated configs
 class V4096Ara2LaneRocketConfig extends Config(
   new ara.WithAraRocketVectorUnit(4096, 2) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 
 class V8192Ara4LaneRocketConfig extends Config(
   new ara.WithAraRocketVectorUnit(8192, 4) ++
   new chipyard.config.WithSystemBusWidth(128) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index 08aab4c0e3..33eb5aac9b 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -17,7 +17,7 @@ class ChipLikeRocketConfig extends Config(
   // Set up tiles
   //==================================
   new freechips.rocketchip.rocket.WithAsynchronousCDCs(depth=8, sync=3) ++ // Add async crossings between RocketTile and uncore
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++                      // 1 RocketTile
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++                      // 1 RocketTile
 
   //==================================
   // Set up I/O
diff --git a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
index da65d9d1cb..dd1b09eb58 100644
--- a/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipletConfigs.scala
@@ -35,7 +35,7 @@ class SymmetricChipletRocketConfig extends Config(
     replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
   ) ++
   new testchipip.soc.WithOffchipBus ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
@@ -71,7 +71,7 @@ class RocketCoreChipletConfig extends Config(
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // LLC-only chiplet
diff --git a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala
index 837e732eeb..f35817729d 100644
--- a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala
@@ -14,7 +14,7 @@ import testchipip.soc.{OBUS}
 // Note: This is what designs inheriting from AbstractConfig do by default
 class DefaultClockingRocketConfig extends Config(
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This is a more physically realistic approach, normally we can't punch out a separate
@@ -23,12 +23,12 @@ class DefaultClockingRocketConfig extends Config(
 // clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info
 class ChipLikeClockingRocketConfig extends Config(
   new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single
 // clock input pin.
 class SingleClockBroadcastRocketConfig extends Config(
   new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
index 1d344ee543..9252ba6b29 100644
--- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
@@ -8,20 +8,20 @@ import org.chipsalliance.cde.config.{Config}
 
 class LargeBoomAndRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(1) ++                    // single-core boom
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++         // single rocket-core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class DualLargeBoomAndDualRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
-  new freechips.rocketchip.rocket.WithNBigCores(2) ++  // add 2 rocket cores
+  new freechips.rocketchip.rocket.WithNHugeCores(2) ++  // add 2 rocket cores
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DualBoomAndSingleRocket
 class DualLargeBoomAndSingleRocketConfig extends Config(
   new boom.v3.common.WithNLargeBooms(2) ++             // add 2 boom cores
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++  // add 1 rocket core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++  // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DualBoomAndSingleRocket
@@ -29,6 +29,6 @@ class DualLargeBoomAndSingleRocketConfig extends Config(
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
   new freechips.rocketchip.rocket.WithNSmallCores(1) ++    // Add a small "control" core
   new boom.v3.common.WithNLargeBooms(1) ++                 // Add 1 boom core
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++      // add 1 rocket core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++      // add 1 rocket core
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
index eaae215ae9..30a180439f 100644
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -10,51 +10,51 @@ import org.chipsalliance.cde.config.{Config}
 class FFTRocketConfig extends Config(
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++              // TODO: hack around dontTouch not working in SFC
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: FFTRocketConfig
 
 // DOC include start: GCDTLRocketConfig
 class GCDTLRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDTLRocketConfig
 
 // DOC include start: GCDAXI4BlackBoxRocketConfig
 class GCDAXI4BlackBoxRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++            // Use GCD blackboxed verilog, connect by AXI4->Tilelink
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GCDAXI4BlackBoxRocketConfig
 
 // DOC include start: InitZeroRocketConfig
 class InitZeroRocketConfig extends Config(
   new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++   // add InitZero
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: InitZeroRocketConfig
 
 class StreamingPassthroughRocketConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: StreamingFIRRocketConfig
 class StreamingFIRRocketConfig extends Config (
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: StreamingFIRRocketConfig
 
 class SmallNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("small") ++               // add a small NVDLA
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class LargeNVDLARocketConfig extends Config(
   new nvidia.blocks.dla.WithNVDLA("large", true) ++         // add a large NVDLA with synth. rams
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class ManyMMIOAcceleratorRocketConfig extends Config(
@@ -63,5 +63,5 @@ class ManyMMIOAcceleratorRocketConfig extends Config(
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
   new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
   new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
index 2162435c97..0ec6fe23ef 100644
--- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
@@ -8,38 +8,38 @@ import org.chipsalliance.cde.config.{Config}
 
 class SimAXIRocketConfig extends Config(
   new chipyard.harness.WithSimAXIMem ++                     // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class GB1MemoryRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadOnlyRocketConfig extends Config(
   new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: mbusscratchpadrocket
 
 class SbusScratchpadRocketConfig extends Config(
   new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SbusBypassRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++ // Add bypass path to access DRAM incoherently through an address alias
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class QuadChannelRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++      // 4 AXI4 channels
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BroadcastCoherenceRocketConfig extends Config(
   new chipyard.config.WithBroadcastManager ++                 // Use broadcast-based coherence hub
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index 76838d56d3..22e0c55357 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -101,7 +101,7 @@ class MultiNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(8) { UserVirtualChannelParams(4) }),
       routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(Mesh2DEscapeRouting()), 5, 1))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
   new chipyard.config.AbstractConfig
@@ -180,7 +180,7 @@ class SharedNoCConfig extends Config(
         "system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6,
         "pbus" -> 4))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
   new chipyard.config.AbstractConfig
@@ -216,7 +216,7 @@ class SbusRingNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }),
       routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(8) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(8) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.AbstractConfig
 )
@@ -260,7 +260,7 @@ class SbusMeshNoCConfig extends Config(
     ),
     beDivision = 4
   ), inlineNoC = true) ++
-  new freechips.rocketchip.rocket.WithNBigCores(12) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(12) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig
@@ -286,6 +286,6 @@ class QuadRocketSbusRingNoCConfig extends Config(
       channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
       routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
   )) ++
-  new freechips.rocketchip.rocket.WithNBigCores(4) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(4) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
index 97097c8eaf..5a4712c4fe 100644
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -10,44 +10,44 @@ import freechips.rocketchip.subsystem.{MBUS}
 class LargeSPIFlashROMRocketConfig extends Config(
   new chipyard.harness.WithSimSPIFlashModel(true) ++        // add the SPI flash model in the harness (read-only)
   new chipyard.config.WithSPIFlash ++                       // add the SPI flash controller
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SmallSPIFlashRocketConfig extends Config(
   new chipyard.harness.WithSimSPIFlashModel(false) ++       // add the SPI flash model in the harness (writeable)
   new chipyard.config.WithSPIFlash(0x100000) ++             // add the SPI flash controller (1 MiB)
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SimBlockDeviceRocketConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++                // drive block-device IOs with SimBlockDevice
   new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to peripherybus
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
   new chipyard.harness.WithBlockDeviceModel ++              // drive block-device IOs with a BlockDeviceModel
   new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to periphery bus
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: GPIORocketConfig
 class GPIORocketConfig extends Config(
   new chipyard.config.WithGPIO ++                           // add GPIOs to the peripherybus
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GPIORocketConfig
 
 class LoopbackNICRocketConfig extends Config(
   new chipyard.harness.WithLoopbackNIC ++                      // drive NIC IOs with loopback
   new icenet.WithIceNIC ++                                     // add an IceNIC
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class MMIORocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class LBWIFRocketConfig extends Config(
@@ -56,14 +56,14 @@ class LBWIFRocketConfig extends Config(
   new testchipip.soc.WithOffchipBus ++
   new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove AXI4 backing memory
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: DmiRocket
 
@@ -75,7 +75,7 @@ class dmiCospikeCheckpointingRocketConfig extends Config(
   new chipyard.config.WithNPMPs(0) ++                   // remove PMPs (reduce non-core arch state)
   new freechips.rocketchip.rocket.WithDebugROB ++       // cospike needs wdata given by the unsynth. debug rom
   new freechips.rocketchip.rocket.WithCease(false) ++   // remove xrocket ISA extension
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 
@@ -91,7 +91,7 @@ class ManyPeripheralsRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
   new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
   new freechips.rocketchip.subsystem.WithNoMemPort ++        // remove AXI4 backing memory
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class UARTTSIRocketConfig extends Config(
@@ -100,5 +100,5 @@ class UARTTSIRocketConfig extends Config(
   new chipyard.config.WithMemoryBusFrequency(10) ++
   new chipyard.config.WithFrontBusFrequency(10) ++
   new chipyard.config.WithPeripheryBusFrequency(10) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
index 6e210e0bc6..7b2de98c99 100644
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -9,26 +9,26 @@ import org.chipsalliance.cde.config.{Config}
 // DOC include start: GemminiRocketConfig
 class GemminiRocketConfig extends Config(
   new gemmini.DefaultGemminiConfig ++                            // use Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: GemminiRocketConfig
 
 class FPGemminiRocketConfig extends Config(
   new gemmini.GemminiFP32DefaultConfig ++                         // use FP32Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class LeanGemminiRocketConfig extends Config(
   new gemmini.LeanGemminiConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
 class LeanGemminiPrintfRocketConfig extends Config(
   new gemmini.LeanGemminiPrintfConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.WithSystemBusWidth(128) ++
   new chipyard.config.AbstractConfig)
 
@@ -39,12 +39,12 @@ class MempressRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBanks(8) ++
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=16, capacityKB=2048) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class AES256ECBRocketConfig extends Config(
   new aes.WithAES256ECBAccel ++                                   // use Caliptra AES 256 ECB accelerator
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.WithSystemBusWidth(256) ++
   new chipyard.config.AbstractConfig)
 
@@ -55,7 +55,7 @@ class ReRoCCTestConfig extends Config(
   new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile2 is accum
   new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile1 is accum
   new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile0 is accum
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class ReRoCCManyGemminiConfig extends Config(
@@ -64,10 +64,10 @@ class ReRoCCManyGemminiConfig extends Config(
   new gemmini.LeanGemminiConfig ++                              // rerocc tile2 is gemmini
   new gemmini.LeanGemminiConfig ++                              // rerocc tile1 is gemmini
   new gemmini.LeanGemminiConfig ++                              // rerocc tile0 is gemmini
-  new freechips.rocketchip.rocket.WithNBigCores(4) ++           // 4 rocket cores
+  new freechips.rocketchip.rocket.WithNHugeCores(4) ++           // 4 rocket cores
   new chipyard.config.AbstractConfig)
 
 class ZstdCompressorRocketConfig extends Config(
   new compressacc.WithZstdCompressor ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index cefeb6f929..e9e4b2c4b5 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -9,11 +9,11 @@ import freechips.rocketchip.subsystem.{InCluster}
 // --------------
 
 class RocketConfig extends Config(
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
 class DualRocketConfig extends Config(
-  new freechips.rocketchip.rocket.WithNBigCores(2) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(2) ++
   new chipyard.config.AbstractConfig)
 
 class TinyRocketConfig extends Config(
@@ -26,17 +26,17 @@ class TinyRocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class QuadRocketConfig extends Config(
-  new freechips.rocketchip.rocket.WithNBigCores(4) ++    // quad-core (4 RocketTiles)
+  new freechips.rocketchip.rocket.WithNHugeCores(4) ++    // quad-core (4 RocketTiles)
   new chipyard.config.AbstractConfig)
 
 class Cloned64RocketConfig extends Config(
   new freechips.rocketchip.rocket.WithCloneRocketTiles(63, 0) ++ // copy tile0 63 more times
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++            // tile0 is a BigRocket
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++            // tile0 is a BigRocket
   new chipyard.config.AbstractConfig)
 
 class RV32RocketConfig extends Config(
   new freechips.rocketchip.rocket.WithRV32 ++            // set RocketTiles to be 32-bit
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // DOC include start: l1scratchpadrocket
@@ -46,7 +46,7 @@ class ScratchpadOnlyRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // remove offchip mem port
   new freechips.rocketchip.rocket.WithScratchpadsOnly ++       // use rocket l1 DCache scratchpad as base phys mem
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: l1scratchpadrocket
 
@@ -58,18 +58,18 @@ class MMIOScratchpadOnlyRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // remove offchip mem port
   new freechips.rocketchip.rocket.WithScratchpadsOnly ++       // use rocket l1 DCache scratchpad as base phys mem
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class L1ScratchpadRocketConfig extends Config(
   new chipyard.config.WithRocketICacheScratchpad ++         // use rocket ICache scratchpad
   new chipyard.config.WithRocketDCacheScratchpad ++         // use rocket DCache scratchpad
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class MulticlockRocketConfig extends Config(
   new freechips.rocketchip.rocket.WithAsynchronousCDCs(8, 3) ++ // Add async crossings between RocketTile and uncore
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   // Frequency specifications
   new chipyard.config.WithTileFrequency(1000.0) ++        // Matches the maximum frequency of U540
   new chipyard.clocking.WithClockGroupsCombinedByName(("uncore"   , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil),
@@ -87,7 +87,7 @@ class CustomIOChipTopRocketConfig extends Config(
   new chipyard.example.WithBrokenOutUARTIO ++
   new chipyard.example.WithCustomChipTop ++
   new chipyard.example.WithCustomIOCells ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++         // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
 class PrefetchingRocketConfig extends Config(
@@ -96,22 +96,22 @@ class PrefetchingRocketConfig extends Config(
   new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++                // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2
   new chipyard.config.WithTilePrefetchers ++                                           // add TL prefetchers between tiles and the sbus
   new freechips.rocketchip.rocket.WithL1DCacheNonblocking(2) ++                        // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++                                  // single rocket-core
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++                                  // single rocket-core
   new chipyard.config.AbstractConfig)
 
 class ClusteredRocketConfig extends Config(
-  new freechips.rocketchip.rocket.WithNBigCores(4, location=InCluster(1)) ++
-  new freechips.rocketchip.rocket.WithNBigCores(4, location=InCluster(0)) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(4, location=InCluster(1)) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(4, location=InCluster(0)) ++
   new freechips.rocketchip.subsystem.WithCluster(1) ++
   new freechips.rocketchip.subsystem.WithCluster(0) ++
   new chipyard.config.AbstractConfig)
 
 class FastRTLSimRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class SV48RocketConfig extends Config(
   new freechips.rocketchip.rocket.WithSV48 ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/SaturnConfigs.scala b/generators/chipyard/src/main/scala/config/SaturnConfigs.scala
index 4ff761c1bf..9663b96a19 100644
--- a/generators/chipyard/src/main/scala/config/SaturnConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SaturnConfigs.scala
@@ -6,52 +6,52 @@ import saturn.common.{VectorParams}
 // Rocket-integrated configs
 class MINV64D64RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(64, 64, VectorParams.minParams) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class MINV128D64RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class MINV256D64RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.minParams) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class REFV128D128RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(128, 128, VectorParams.refParams) ++
   new chipyard.config.WithSystemBusWidth(128) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class REFV256D64RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(256, 64, VectorParams.refParams) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class REFV256D128RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(256, 128, VectorParams.refParams) ++
   new chipyard.config.WithSystemBusWidth(128) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class REFV512D128RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(512, 128, VectorParams.refParams) ++
   new chipyard.config.WithSystemBusWidth(128) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class REFV512D256RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(512, 256, VectorParams.refParams) ++
   new chipyard.config.WithSystemBusWidth(256) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class DMAV256D256RocketConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(256, 256, VectorParams.dmaParams) ++
   new chipyard.config.WithSystemBusWidth(256) ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // Shuttle-integrated configs
@@ -156,7 +156,7 @@ class MINV128D64RocketCosimConfig extends Config(
   new saturn.rocket.WithRocketVectorUnit(128, 64, VectorParams.minParams) ++
   new freechips.rocketchip.rocket.WithCease(false) ++
   new freechips.rocketchip.rocket.WithDebugROB ++
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class GENV256D128ShuttleCosimConfig extends Config(
diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
index dd3175cbc7..e5b22d587f 100644
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -27,7 +27,7 @@ class TutorialStarterConfig extends Config(
   // CUSTOMIZE THE CORE
   // Uncomment out one (or multiple) of the lines below, and choose
   // how many cores you want.
-  // new freechips.rocketchip.rocket.WithNBigCores(1) ++    // Specify we want some number of Rocket cores
+  // new freechips.rocketchip.rocket.WithNHugeCores(1) ++    // Specify we want some number of Rocket cores
   // new boom.v3.common.WithNSmallBooms(1) ++                     // Specify we want some number of BOOM cores
 
   // CUSTOMIZE the L2
@@ -46,7 +46,7 @@ class TutorialMMIOConfig extends Config(
   // new chipyard.example.WithGCD(useAXI4=true) ++  // Use AXI4 version
 
   // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration
-  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig
 )
 
@@ -90,6 +90,6 @@ class TutorialNoCConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++
 
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new freechips.rocketchip.rocket.WithNBigCores(2) ++
+  new freechips.rocketchip.rocket.WithNHugeCores(2) ++
   new chipyard.config.AbstractConfig
 )
diff --git a/generators/saturn b/generators/saturn
index efced6db88..3e7999aee1 160000
--- a/generators/saturn
+++ b/generators/saturn
@@ -1 +1 @@
-Subproject commit efced6db88573b1687a3a889160f19152878f6d2
+Subproject commit 3e7999aee13b9b6d3dbd310d9ca98c20ed5bc098

From 9af401d31d7e7dbb2d0a9c1723d054202c4eae3f Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 19:54:02 -0700
Subject: [PATCH 7/9] Serialize CI to improve debuggability

---
 .github/scripts/run-tests.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index 30ebb5d0e0..8a75285019 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -13,11 +13,11 @@ DISABLE_SIM_PREREQ="BREAK_SIM_PREREQ=1"
 MAPPING_FLAGS=${mapping[$1]}
 
 run_bmark () {
-    make run-bmark-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
+    make run-bmark-tests-fast -j1 -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }
 
 run_asm () {
-    make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
+    make run-asm-tests-fast -j1 -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }
 
 run_tracegen () {

From 5a3c660bb418c5fdd5ca5d059b5b826b8d2a07c5 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 19:57:11 -0700
Subject: [PATCH 8/9] Use Spike w. zicntr for riscv-asm-tests

Our configs implement partial zicntr and do not provide the isa string zicntr.
We want spike to match our configs, but partial zicntr is not provided in spike.
For CI, enable full zicntr for spike
---
 .github/scripts/defaults.sh                   |  2 +-
 .../chipyard/src/main/scala/SpikeTile.scala   | 19 +++++++++++++++++--
 .../src/main/scala/config/SpikeConfigs.scala  |  5 +++++
 3 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index 8d39785260..8a9e8f7622 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -50,7 +50,7 @@ mapping["chipyard-boomv3"]=" CONFIG=MediumBoomV3CosimConfig"
 mapping["chipyard-dmiboomv3"]=" CONFIG=dmiCheckpointingMediumBoomV3Config"
 mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
 mapping["chipyard-dmiboomv4"]=" CONFIG=dmiCheckpointingMediumBoomV4Config"
-mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
+mapping["chipyard-spike"]=" CONFIG=SpikeZicntrConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
 mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
 mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index b6f3627748..f375b099cb 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -17,7 +17,8 @@ import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
 case class SpikeCoreParams(
-  nPMPs: Int = 16
+  nPMPs: Int = 16,
+  useZicntr: Boolean = false
 ) extends CoreParams {
   val xLen = 64
   val pgLevels = 5
@@ -120,7 +121,17 @@ class SpikeTile(
   val slaveNode = TLIdentityNode()
 
   // Note: Rocket doesn't support zicntr but Spike does (err on the side of having Rocket's ISA)
-  override def isaDTS = "rv64imafdcbv_zicsr_zifencei_zihpm_zvl128b_zve64d_zba_zbb_zbs"
+  override def isaDTS = (Seq(
+    "rv64imafdcbv",
+    "zicsr",
+    "zifencei",
+    "zihpm",
+    "zvl128b",
+    "zve64d",
+    "zba",
+    "zbb",
+    "zbs"
+  ) ++ spikeTileParams.core.useZicntr.option("zicntr")).mkString("_")
 
   // Required entry of CPU device in the device tree for interrupt purpose
   val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("ucb-bar,spike", "riscv")) {
@@ -473,6 +484,10 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
   }
 }
 
+class WithSpikeZicntr extends TileAttachConfig[SpikeTileAttachParams](t =>
+  t.copy(tileParams=t.tileParams.copy(core=t.tileParams.core.copy(useZicntr=true)))
+)
+
 class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams()
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
index 368d4745ea..7d588a363a 100644
--- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
@@ -10,6 +10,11 @@ class SpikeConfig extends Config(
   new chipyard.WithNSpikeCores(1) ++
   new chipyard.config.AbstractConfig)
 
+class SpikeZicntrConfig extends Config(
+  new chipyard.WithSpikeZicntr ++
+  new chipyard.WithNSpikeCores(1) ++
+  new chipyard.config.AbstractConfig)
+
 class dmiSpikeConfig extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tilelink
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port

From 7aa81f1fe107e0ada958187439cd76d13c75dd64 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 13 Aug 2024 21:59:22 -0700
Subject: [PATCH 9/9] Fix boom cosim

---
 generators/boom       | 2 +-
 generators/testchipip | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/generators/boom b/generators/boom
index 64dae5bd32..d2a64f7ca9 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 64dae5bd3248c3c49b805d2d08848838356fe373
+Subproject commit d2a64f7ca9fd914d9c686cb23edcd32d3465a02e
diff --git a/generators/testchipip b/generators/testchipip
index 541864d602..c94c1e3fa9 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 541864d602ba9021e0256d7bf0da2a2a25acdb91
+Subproject commit c94c1e3fa9f7437a3e95f63181cf0f54b8650b3a