Failed to finish Sky130 + OpenROAD Tutorial(chipyard1.11.0)

[DecodeTheEncoded]

I am following the Sky130+OpenRoad tutorial using chipyard 1.11.0, I followed the exact instructions in the documentation, and install all the prequsities without error. However, When I make buildfile tutorial=sky130-openroad, the terminal has the following error:

(/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env) ➜  vlsi git:(ac58f38d) ✗ make buildfile tutorial=sky130-openroad
Running with RISCV=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/riscv-tools
echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/generators | grep ^-
Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer && java -jar /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/scripts/sbt-launch.jar -Dsbt.ivy.home=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.ivy2 -Dsbt.global.base=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.sbt -Dsbt.boot.directory=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.sbt/boot/ -Dsbt.color=always -Dsbt.supershell=false -Dsbt.server.forcestart=true ";project chipyard; set assembly / assemblyOutputPath := file(\"/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/chipyard.jar\"); assembly" && touch /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/chipyard.jar
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.java_tmp
[info] welcome to sbt 1.8.2 (N/A Java 20.0.2-internal)
[info] loading settings for project miaosuancomputer-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project barf from build.sbt ...
[info] loading settings for project constellation from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project ibex from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project tapeout from build.sbt ...
[info] loading settings for project fixedpoint from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] resolving key references (41633 settings) ...
[info] set current project to chipyardRoot (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/)
[info] set current project to chipyard (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/)
[info] Defining assembly / assemblyOutputPath
[info] The new value will be used by assembly
[info] Reapplying settings...
[info] set current project to chipyard (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/)
[warn] multiple main classes detected: run 'show discoveredMainClasses' to see the list
[info] 185 file(s) merged using strategy 'Rename (Custom)' (Run the task at debug level to see the details)
[info] 61 file(s) merged using strategy 'Rename' (Run the task at debug level to see the details)
[info] 168 file(s) merged using strategy 'Discard' (Run the task at debug level to see the details)
[info] 4 file(s) merged using strategy 'FilterDistinctLines' (Run the task at debug level to see the details)
[info] Built: /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/chipyard.jar
[info] Jar hash: 83769bf3fa5b4347a6d87a9f4a77ad4c0ed366c9
[success] Total time: 23 s, completed Jul 12, 2024, 10:59:57 AM
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer && java -jar /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/scripts/sbt-launch.jar -Dsbt.ivy.home=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.ivy2 -Dsbt.global.base=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.sbt -Dsbt.boot.directory=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.sbt/boot/ -Dsbt.color=always -Dsbt.supershell=false -Dsbt.server.forcestart=true ";project tapeout; set assembly / assemblyOutputPath := file(\"/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/tapeout.jar\"); assembly" && touch /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/tapeout.jar
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.java_tmp
[info] welcome to sbt 1.8.2 (N/A Java 20.0.2-internal)
[info] loading settings for project miaosuancomputer-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project barf from build.sbt ...
[info] loading settings for project constellation from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project ibex from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project tapeout from build.sbt ...
[info] loading settings for project fixedpoint from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] resolving key references (41633 settings) ...
[info] set current project to chipyardRoot (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/)
[info] set current project to tapeout (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/)
[info] Defining assembly / assemblyOutputPath
[info] The new value will be used by assembly
[info] Reapplying settings...
[info] set current project to tapeout (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/)
[warn] multiple main classes detected: run 'show discoveredMainClasses' to see the list
[info] 185 file(s) merged using strategy 'Rename (Custom)' (Run the task at debug level to see the details)
[info] 18 file(s) merged using strategy 'Rename' (Run the task at debug level to see the details)
[info] 71 file(s) merged using strategy 'Discard' (Run the task at debug level to see the details)
[info] 4 file(s) merged using strategy 'FilterDistinctLines' (Run the task at debug level to see the details)
[info] Built: /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/tapeout.jar
[info] Jar hash: 6ac68f311c5008d9387f205f3f63d979ceb1b9ec
[success] Total time: 4 s, completed Jul 12, 2024, 11:00:14 AM
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig
cp -f /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.rv64.img /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/bootrom.rv64.img
cp -f /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.rv32.img /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/bootrom.rv32.img
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig
(set -o pipefail && 	cd /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer && java -cp /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/chipyard.jar chipyard.Generator  --target-dir /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig --name chipyard.harness.TestHarness.TinyRocketConfig --top-module chipyard.harness.TestHarness --legacy-configs chipyard:TinyRocketConfig   | tee /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.chisel.log)
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.java_tmp
WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
Interrupt map (1 harts 1 interrupts):
  [1, 1] => uart_0

WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
<stdin>:52.18-57.5: Warning (simple_bus_reg): /soc/cbus_clock: missing or empty reg/ranges property
<stdin>:84.18-89.5: Warning (simple_bus_reg): /soc/fbus_clock: missing or empty reg/ranges property
<stdin>:100.18-105.5: Warning (simple_bus_reg): /soc/pbus_clock: missing or empty reg/ranges property
<stdin>:111.18-116.5: Warning (simple_bus_reg): /soc/sbus_clock: missing or empty reg/ranges property
<stdin>:33.29-37.6: Warning (interrupt_provider): /cpus/cpu@0/interrupt-controller: Missing #address-cells in interrupt provider
<stdin>:90.37-99.5: Warning (interrupt_provider): /soc/interrupt-controller@c000000: Missing #address-cells in interrupt provider
WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
Clock sbus_0: using diplomatically specified frequency of 500.0.
Clock pbus_0: using diplomatically specified frequency of 500.0.
Clock fbus_0: using diplomatically specified frequency of 500.0.
Clock cbus_0: using diplomatically specified frequency of 500.0.
WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
WARNING: TLMonitor instantiated on a bus with source bits (15) > 14; A=>D transaction flight will not be checked
/dts-v1/;

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "ucb-bar,chipyard-dev";
	model = "ucb-bar,chipyard";
	L26: aliases {
		serial0 = &L20;
	};
	L13: chosen {
		stdout-path = &L20;
	};
	L25: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <1000000>;
		L8: cpu@0 {
			clock-frequency = <0>;
			compatible = "sifive,rocket0", "riscv";
			device_type = "cpu";
			hardware-exec-breakpoint-count = <1>;
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <4096>;
			reg = <0x0>;
			riscv,isa = "rv32imaczicsr_zifencei_zihpm_xrocket";
			riscv,pmpgranularity = <4>;
			riscv,pmpregions = <8>;
			sifive,dtim = <&L7>;
			status = "okay";
			timebase-frequency = <1000000>;
			L5: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};
	};
	L27: htif {
		compatible = "ucb,htif0";
	};
	L24: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "ucb-bar,chipyard-soc", "simple-bus";
		ranges;
		L19: boot-address-reg@1000 {
			reg = <0x1000 0x1000>;
			reg-names = "control";
		};
		L3: cbus_clock {
			#clock-cells = <0>;
			clock-frequency = <500000000>;
			clock-output-names = "cbus_clock";
			compatible = "fixed-clock";
		};
		L9: clint@2000000 {
			compatible = "riscv,clint0";
			interrupts-extended = <&L5 3 &L5 7>;
			reg = <0x2000000 0x10000>;
			reg-names = "control";
		};
		L21: clock-gater@100000 {
			reg = <0x100000 0x1000>;
			reg-names = "control";
		};
		L11: debug-controller@0 {
			compatible = "sifive,debug-013", "riscv,debug-013";
			debug-attach = "jtag";
			interrupts-extended = <&L5 65535>;
			reg = <0x0 0x1000>;
			reg-names = "control";
		};
		L7: dtim@80000000 {
			compatible = "sifive,dtim0";
			reg = <0x80000000 0x4000>;
			reg-names = "mem";
		};
		L4: error-device@3000 {
			compatible = "sifive,error0";
			reg = <0x3000 0x1000>;
		};
		L2: fbus_clock {
			#clock-cells = <0>;
			clock-frequency = <500000000>;
			clock-output-names = "fbus_clock";
			compatible = "fixed-clock";
		};
		L10: interrupt-controller@c000000 {
			#interrupt-cells = <1>;
			compatible = "riscv,plic0";
			interrupt-controller;
			interrupts-extended = <&L5 11>;
			reg = <0xc000000 0x4000000>;
			reg-names = "control";
			riscv,max-priority = <1>;
			riscv,ndev = <1>;
		};
		L1: pbus_clock {
			#clock-cells = <0>;
			clock-frequency = <500000000>;
			clock-output-names = "pbus_clock";
			compatible = "fixed-clock";
		};
		L18: rom@10000 {
			compatible = "sifive,rom0";
			reg = <0x10000 0x10000>;
			reg-names = "mem";
		};
		L0: sbus_clock {
			#clock-cells = <0>;
			clock-frequency = <500000000>;
			clock-output-names = "sbus_clock";
			compatible = "fixed-clock";
		};
		L20: serial@10020000 {
			clocks = <&L1>;
			compatible = "sifive,uart0";
			interrupt-parent = <&L10>;
			interrupts = <1>;
			reg = <0x10020000 0x1000>;
			reg-names = "control";
		};
		L22: tile-reset-setter@110000 {
			reg = <0x110000 0x1000>;
			reg-names = "control";
		};
	};
};

Generated Address Map
	       0 -     1000 ARWX  debug-controller@0
	    1000 -     2000 ARW   boot-address-reg@1000
	    3000 -     4000 ARWX  error-device@3000
	   10000 -    20000  R X  rom@10000
	  100000 -   101000 ARW   clock-gater@100000
	  110000 -   111000 ARW   tile-reset-setter@110000
	 2000000 -  2010000 ARW   clint@2000000
	 c000000 - 10000000 ARW   interrupt-controller@c000000
	10020000 - 10021000 ARW   serial@10020000
	80000000 - 80004000 ARWX  dtim@80000000

IOCells generated by IOBinders:
  IOBinder for interface sifive.blocks.devices.uart.HasPeripheryUARTModuleImp generated:
    1 X GenericDigitalInIOCell
    1 X GenericDigitalOutIOCell
  IOBinder for interface testchipip.boot.CanHavePeripheryCustomBootPin generated:
    1 X GenericDigitalInIOCell
  IOBinder for interface freechips.rocketchip.devices.debug.HasPeripheryDebug generated:
    3 X GenericDigitalInIOCell
    1 X GenericDigitalOutIOCell
  IOBinder for interface chipyard.clocking.CanHaveClockTap generated:
    1 X GenericDigitalOutIOCell
  IOBinder for interface testchipip.serdes.CanHavePeripheryTLSerial generated:
    35 X GenericDigitalInIOCell
    34 X GenericDigitalOutIOCell

  Total generated 77 IOCells:
    40 X GenericDigitalInIOCell
    37 X GenericDigitalOutIOCell
Harness binder clock is 100.0
[warn] generators/rocket-chip/src/main/scala/tilelink/Monitor.scala:658:26: Dynamic index with width 1 is too large for extractee of width 1
[warn]       monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
[warn]                          ^
[warn] generators/rocket-chip/src/main/scala/tilelink/Monitor.scala:682:25: Dynamic index with width 1 is too large for extractee of width 1
[warn]       assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
[warn]                         ^
[warn] generators/rocket-chip/src/main/scala/tilelink/Monitor.scala:766:26: Dynamic index with width 1 is too large for extractee of width 1
[warn]       monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
[warn]                          ^
[warn] generators/rocket-chip/src/main/scala/tilelink/Monitor.scala:793:25: Dynamic index with width 1 is too large for extractee of width 1
[warn]       assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
[warn]                         ^
[warn] generators/rocket-chip/src/main/scala/rocket/ICache.scala:500:25: Dynamic index with width 7 is too large for extractee of width 64
[warn]     val s1_vb = vb_array(Cat(i.U, s1_idx)) && !s1_slaveValid
[warn]                         ^
[warn] generators/rocket-chip/src/main/scala/rocket/CSR.scala:953:100: Dynamic index with width 8 is too large for extractee of width 32
[warn]   val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_lsbs), read_medeleg(cause_lsbs))
[warn]                                                                                                    ^
[warn] generators/rocket-chip/src/main/scala/rocket/CSR.scala:953:126: Dynamic index with width 8 is too large for extractee of width 32
[warn]   val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_lsbs), read_medeleg(cause_lsbs))
[warn]                                                                                                                              ^
[warn] generators/rocket-chip/src/main/scala/rocket/CSR.scala:954:80: Dynamic index with width 8 is too large for extractee of width 32
[warn]   val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_lsbs), read_hedeleg(cause_lsbs))
[warn]                                                                                ^
[warn] generators/rocket-chip/src/main/scala/rocket/CSR.scala:954:106: Dynamic index with width 8 is too large for extractee of width 32
[warn]   val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_lsbs), read_hedeleg(cause_lsbs))
[warn]                                                                                                          ^
[warn] generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1729:37: Dynamic index with width 1 is too large for extractee of width 1
[warn]     val hartHalted   = haltedBitRegs(selectedHartReg)
[warn]                                     ^
[warn] There were 10 warning(s) during hardware elaboration.
echo "$mfc_extra_anno_contents" > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.extrafirtool.anno.json
echo "$sfc_extra_low_transforms_anno_contents" > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.extrasfc.anno.json
jq -s '[.[][]]' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.anno.json /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.extrafirtool.anno.json > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.extra.anno.json
echo  none > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/.sfc_level
echo ""  > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/.extra_firrtl_options
if [ none = low ]; then jq -s '[.[][]]' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.extra.anno.json /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.extrasfc.anno.json > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.appended.anno.json; fi
if [ none = none ]; then cat /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.extra.anno.json > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.appended.anno.json; fi
touch /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.appended.anno.json
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/
echo "emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket,disallowPackedArrays" > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/.mfc_lowering_options
rm -rf /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer && java -cp /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/tapeout.jar barstools.tapeout.transforms.GenerateModelStageMain  --no-dedup --output-file /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc --output-annotation-file /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.anno.json --target-dir /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral --input-file /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.fir --annotation-file /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.appended.anno.json --log-level error --allow-unrecognized-annotations -X none 
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.java_tmp
mv /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.lo.fir /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.fir 2> /dev/null # Optionally change file type when SFC generates LowFIRRTL
make: [/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/common.mk:236: /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/model_module_hierarchy.json] Error 1 (ignored)
firtool \
	--format=fir \
	--export-module-hierarchy \
	--verify-each=true \
	--warn-on-unprocessed-annotations \
	--disable-annotation-classless \
	--disable-annotation-unknown \
	--mlir-timing \
	--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket,disallowPackedArrays \
	--repl-seq-mem \
	--repl-seq-mem-file=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.mems.conf \
	--annotation-file=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.anno.json \
	--split-verilog \
	-o /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral \
	/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.fir
/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.fir:2:1: warning: unprocessed annotation:'firrtl.transforms.NoCircuitDedupAnnotation$' still remaining after LowerToHW
circuit TestHarness :
^
/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.fir:2:1: warning: unprocessed annotation:'logger.LogLevelAnnotation' still remaining after LowerToHW
circuit TestHarness :
^
/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.fir:35924:3: warning: unprocessed annotation:'freechips.rocketchip.util.RegFieldDescMappingAnnotation' still remaining after LowerToHW
  module PeripheryBus :
  ^
/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.fir:131787:3: warning: unprocessed annotation:'freechips.rocketchip.util.ParamsAnnotation' still remaining after LowerToHW
  module RocketTile :
  ^
/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.fir:242410:3: warning: unprocessed annotation:'freechips.rocketchip.util.AddressMapAnnotation' still remaining after LowerToHW
  module DigitalTop :
  ^
generators/rocket-chip/src/main/scala/util/DescribedSRAM.scala:17:26: warning: unprocessed annotation:'freechips.rocketchip.util.SRAMAnnotation' still remaining after LowerToHW
===-------------------------------------------------------------------------===
                         ... Execution time report ...
===-------------------------------------------------------------------------===
  Total Execution Time: 6.4370 seconds

  ----User Time----  ----Wall Time----  ----Name----
    0.8983 (  7.6%)    0.8983 ( 14.0%)  FIR Parser
    0.0376 (  0.3%)    0.0376 (  0.6%)    Parse annotations
    0.0000 (  0.0%)    0.0000 (  0.0%)    Parse OMIR
    0.6569 (  5.5%)    0.6569 ( 10.2%)    Parse modules
    0.1798 (  1.5%)    0.1798 (  2.8%)    Verify circuit
    8.2207 ( 69.3%)    4.1653 ( 64.7%)  'firrtl.circuit' Pipeline
    0.0191 (  0.2%)    0.0191 (  0.3%)    LowerOpenAggs
    0.1837 (  1.5%)    0.1837 (  2.9%)    ResolvePaths
    0.0080 (  0.1%)    0.0080 (  0.1%)      (A) circt::firrtl::InstanceGraph
    0.1446 (  1.2%)    0.1446 (  2.2%)    LowerFIRRTLAnnotations
    0.0072 (  0.1%)    0.0072 (  0.1%)    LowerIntrinsics
    0.0071 (  0.1%)    0.0071 (  0.1%)      (A) circt::firrtl::InstanceGraph
    0.0000 (  0.0%)    0.0000 (  0.0%)    InjectDUTHierarchy
    1.3828 ( 11.7%)    0.4461 (  6.9%)    'firrtl.module' Pipeline
    0.6908 (  5.8%)    0.1846 (  2.9%)      DropName
    0.3926 (  3.3%)    0.1505 (  2.3%)      CSE
    0.0006 (  0.0%)    0.0002 (  0.0%)        (A) DominanceInfo
    0.0529 (  0.4%)    0.0150 (  0.2%)      LowerCHIRRTLPass
    0.2429 (  2.0%)    0.0954 (  1.5%)      LowerMatches
    0.2988 (  2.5%)    0.2988 (  4.6%)    InferWidths
    0.0001 (  0.0%)    0.0001 (  0.0%)      (A) SymbolTable
    0.0107 (  0.1%)    0.0107 (  0.2%)      (A) circt::hw::InnerSymbolTableCollection
    0.1526 (  1.3%)    0.1526 (  2.4%)    MemToRegOfVec
    0.1998 (  1.7%)    0.1998 (  3.1%)    InferResets
    0.0085 (  0.1%)    0.0085 (  0.1%)      (A) circt::firrtl::InstanceGraph
    0.1329 (  1.1%)    0.1329 (  2.1%)    DropConst
    0.0003 (  0.0%)    0.0003 (  0.0%)    HoistPassthrough
    0.0071 (  0.1%)    0.0071 (  0.1%)    ProbeDCE
    0.2720 (  2.3%)    0.2720 (  4.2%)    Dedup
    0.0003 (  0.0%)    0.0003 (  0.0%)      (A) circt::firrtl::NLATable
    0.0001 (  0.0%)    0.0001 (  0.0%)      (A) SymbolTable
    0.0316 (  0.3%)    0.0316 (  0.5%)    WireDFT
    0.2493 (  2.1%)    0.0865 (  1.3%)    'firrtl.module' Pipeline
    0.2484 (  2.1%)    0.0864 (  1.3%)      FlattenMemory
    0.2463 (  2.1%)    0.2463 (  3.8%)    LowerFIRRTLTypes
    0.0000 (  0.0%)    0.0000 (  0.0%)      (A) SymbolTable
    0.3790 (  3.2%)    0.1118 (  1.7%)    'any' Pipeline
    0.3783 (  3.2%)    0.1117 (  1.7%)      ExpandWhens
    0.7148 (  6.0%)    0.2661 (  4.1%)    'firrtl.module' Pipeline
    0.1871 (  1.6%)    0.0780 (  1.2%)      SFCCompat
    0.2687 (  2.3%)    0.0948 (  1.5%)      LayerMerge
    0.2575 (  2.2%)    0.0931 (  1.4%)      LayerSink
    0.0004 (  0.0%)    0.0001 (  0.0%)        (A) DominanceInfo
    0.0297 (  0.3%)    0.0297 (  0.5%)    LowerLayers
    0.2435 (  2.1%)    0.2435 (  3.8%)    Inliner
    0.0001 (  0.0%)    0.0001 (  0.0%)      (A) SymbolTable
    0.2971 (  2.5%)    0.0968 (  1.5%)    'firrtl.module' Pipeline
    0.2964 (  2.5%)    0.0968 (  1.5%)      RandomizeRegisterInit
    0.2451 (  2.1%)    0.2451 (  3.8%)    CheckCombLoops
    0.0073 (  0.1%)    0.0073 (  0.1%)      (A) circt::firrtl::InstanceGraph
    1.0324 (  8.7%)    0.2803 (  4.4%)    'firrtl.module' Pipeline
    0.9628 (  8.1%)    0.2655 (  4.1%)      Canonicalizer
    0.0689 (  0.6%)    0.0147 (  0.2%)      InferReadWrite
    0.0617 (  0.5%)    0.0617 (  1.0%)    LowerMemory
    0.0028 (  0.0%)    0.0028 (  0.0%)      (A) circt::firrtl::InstanceGraph
    0.0000 (  0.0%)    0.0000 (  0.0%)      (A) SymbolTable
    0.0448 (  0.4%)    0.0448 (  0.7%)    PrefixModules
    0.0033 (  0.0%)    0.0033 (  0.1%)      (A) circt::firrtl::InstanceGraph
    0.0001 (  0.0%)    0.0001 (  0.0%)      (A) circt::firrtl::NLATable
    0.2453 (  2.1%)    0.2453 (  3.8%)    IMConstProp
    0.0039 (  0.0%)    0.0039 (  0.1%)    HoistPassthrough
    0.0027 (  0.0%)    0.0027 (  0.0%)      (A) circt::firrtl::InstanceGraph
    0.1428 (  1.2%)    0.1428 (  2.2%)  IMDeadCodeElim
    0.0029 (  0.0%)    0.0029 (  0.0%)    (A) circt::firrtl::InstanceGraph
    0.0001 (  0.0%)    0.0001 (  0.0%)    (A) SymbolTable
    0.0036 (  0.0%)    0.0036 (  0.1%)    (A) circt::hw::InnerSymbolTableCollection
    0.0017 (  0.0%)    0.0017 (  0.0%)  'firrtl.circuit' Pipeline
    0.0017 (  0.0%)    0.0017 (  0.0%)    AddSeqMemPorts
    0.0016 (  0.0%)    0.0016 (  0.0%)      (A) circt::firrtl::InstanceGraph
    0.0264 (  0.2%)    0.0264 (  0.4%)  CreateSiFiveMetadata
    0.0015 (  0.0%)    0.0015 (  0.0%)    (A) circt::firrtl::InstanceGraph
    0.1151 (  1.0%)    0.1151 (  1.8%)  'firrtl.circuit' Pipeline
    0.0059 (  0.0%)    0.0059 (  0.1%)    ExtractInstances
    0.0014 (  0.0%)    0.0014 (  0.0%)      (A) circt::firrtl::InstanceGraph
    0.0001 (  0.0%)    0.0001 (  0.0%)      (A) circt::firrtl::NLATable
    0.0000 (  0.0%)    0.0000 (  0.0%)    GrandCentral
    0.0268 (  0.2%)    0.0268 (  0.4%)    BlackBoxReader
    0.0823 (  0.7%)    0.0823 (  1.3%)    SymbolDCE
    0.0605 (  0.5%)    0.0605 (  0.9%)  InnerSymbolDCE
    0.3324 (  2.8%)    0.1574 (  2.4%)  'firrtl.circuit' Pipeline
    0.1750 (  1.5%)    0.0280 (  0.4%)    'firrtl.module' Pipeline
    0.1424 (  1.2%)    0.0239 (  0.4%)      Canonicalizer
    0.0316 (  0.3%)    0.0047 (  0.1%)      RegisterOptimizer
    0.1156 (  1.0%)    0.1156 (  1.8%)    IMConstProp
    0.0016 (  0.0%)    0.0016 (  0.0%)      (A) circt::firrtl::InstanceGraph
    0.0973 (  0.8%)    0.0973 (  1.5%)  IMDeadCodeElim
    0.0015 (  0.0%)    0.0015 (  0.0%)    (A) circt::firrtl::InstanceGraph
    0.0000 (  0.0%)    0.0000 (  0.0%)    (A) SymbolTable
    0.0017 (  0.0%)    0.0017 (  0.0%)    (A) circt::hw::InnerSymbolTableCollection
    0.2679 (  2.3%)    0.1434 (  2.2%)  'firrtl.circuit' Pipeline
    0.0000 (  0.0%)    0.0000 (  0.0%)    EmitOMIR
    0.1106 (  0.9%)    0.0185 (  0.3%)    'firrtl.module' Pipeline
    0.0119 (  0.1%)    0.0038 (  0.1%)      MergeConnections
    0.0941 (  0.8%)    0.0165 (  0.3%)      Vectorization
    0.0100 (  0.1%)    0.0100 (  0.2%)    ResolveTraces
    0.0000 (  0.0%)    0.0000 (  0.0%)      (A) circt::firrtl::NLATable
    0.0017 (  0.0%)    0.0017 (  0.0%)      (A) circt::hw::InnerSymbolTableCollection
    0.0299 (  0.3%)    0.0299 (  0.5%)    LowerXMR
    0.0013 (  0.0%)    0.0013 (  0.0%)      (A) circt::firrtl::InstanceGraph
    0.0542 (  0.5%)    0.0542 (  0.8%)    LowerClasses
    0.0016 (  0.0%)    0.0016 (  0.0%)      (A) circt::firrtl::InstanceGraph
    0.0000 (  0.0%)    0.0000 (  0.0%)      (A) SymbolTable
    0.0138 (  0.1%)    0.0019 (  0.0%)    'firrtl.module' Pipeline
    0.0082 (  0.1%)    0.0014 (  0.0%)      Lint
    0.1271 (  1.1%)    0.1271 (  2.0%)  LowerFIRRTLToHW
    0.0017 (  0.0%)    0.0017 (  0.0%)    (A) circt::firrtl::InstanceGraph
    0.0000 (  0.0%)    0.0000 (  0.0%)    (A) circt::firrtl::NLATable
    0.3754 (  3.2%)    0.0573 (  0.9%)  'hw.module' Pipeline
    0.1119 (  0.9%)    0.0149 (  0.2%)    CSE
    0.0004 (  0.0%)    0.0001 (  0.0%)      (A) DominanceInfo
    0.2623 (  2.2%)    0.0423 (  0.7%)    Canonicalizer
    0.0032 (  0.0%)    0.0032 (  0.0%)  VerifyInnerRefNamespace
    0.0036 (  0.0%)    0.0036 (  0.1%)  ExternalizeClockGate
    0.0000 (  0.0%)    0.0000 (  0.0%)    (A) SymbolTable
    0.0757 (  0.6%)    0.0757 (  1.2%)  LowerSeqToSV
    0.0667 (  0.6%)    0.0091 (  0.1%)  'hw.module' Pipeline
    0.0658 (  0.6%)    0.0090 (  0.1%)    LowerVerifToSV
    0.0233 (  0.2%)    0.0233 (  0.4%)  HWMemSimImpl
    0.2936 (  2.5%)    0.0377 (  0.6%)  'hw.module' Pipeline
    0.0970 (  0.8%)    0.0135 (  0.2%)    CSE
    0.0036 (  0.0%)    0.0029 (  0.0%)      (A) DominanceInfo
    0.1179 (  1.0%)    0.0158 (  0.2%)    Canonicalizer
    0.0391 (  0.3%)    0.0053 (  0.1%)    CSE
    0.0002 (  0.0%)    0.0001 (  0.0%)      (A) DominanceInfo
    0.0371 (  0.3%)    0.0049 (  0.1%)    HWCleanup
    0.0033 (  0.0%)    0.0033 (  0.1%)  VerifyInnerRefNamespace
    0.1383 (  1.2%)    0.0216 (  0.3%)  'hw.module' Pipeline
    0.0613 (  0.5%)    0.0125 (  0.2%)    HWLegalizeModules
    0.0759 (  0.6%)    0.0112 (  0.2%)    PrettifyVerilog
    0.0271 (  0.2%)    0.0271 (  0.4%)  StripDebugInfoWithPred
    0.0155 (  0.1%)    0.0155 (  0.2%)  HWExportModuleHierarchy
    0.0000 (  0.0%)    0.0000 (  0.0%)    (A) SymbolTable
    0.0043 (  0.0%)    0.0043 (  0.1%)  VerifyInnerRefNamespace
    0.1550 (  1.3%)    0.1550 (  2.4%)  ExportSplitVerilog
    0.2406 (  2.0%)    0.0482 (  0.7%)  'builtin.module' Pipeline
    0.1924 (  1.6%)    0.0284 (  0.4%)    'hw.module' Pipeline
    0.1917 (  1.6%)    0.0283 (  0.4%)      PrepareForEmission
   -0.0418 ( -0.4%)   -0.0418 ( -0.7%)  Rest
   11.8582 (100.0%)    6.4370 (100.0%)  Total
mv /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.sfc.mems.conf /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.mems.conf 2> /dev/null
make: [/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/common.mk:241: /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/model_module_hierarchy.json] Error 1 (ignored)
sed -i 's/.*/& /' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.mems.conf # need trailing space for SFC macrocompiler
touch /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/firrtl_black_box_resource_files.f # if there are no BB's then the file might not be generated, instead always generate it
/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/scripts/uniquify-module-names.py \
	--model-hier-json /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/model_module_hierarchy.json \
	--top-hier-json /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/top_module_hierarchy.json \
	--in-all-filelist /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/filelist.f \
	--dut ChipTop \
	--model TestHarness \
	--target-dir /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral \
	--out-dut-filelist /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.top.f \
	--out-model-filelist /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.model.f \
	--out-model-hier-json /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/model_module_hierarchy.uniquified.json \
	--gcpath /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/\( \*\)plusarg_reader\( \+\)/\1plusarg_reader_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TestHarness.sv
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/module\( \+\)ResetCatchAndSync_d3/module\1ResetCatchAndSync_d3_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/ResetCatchAndSync_d3_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)ResetCatchAndSync_d3\( \+\)/\1ResetCatchAndSync_d3_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TestHarness.sv
sed -i 's/module\( \+\)UARTRx/module\1UARTRx_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/UARTRx_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)UARTRx\( \+\)/\1UARTRx_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/UARTAdapter.sv
sed -i 's/module\( \+\)UARTTx/module\1UARTTx_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/UARTTx_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)UARTTx\( \+\)/\1UARTTx_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/UARTAdapter.sv
sed -i 's/module\( \+\)AsyncResetSynchronizerShiftReg_w1_d3_i0/module\1AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)AsyncResetSynchronizerShiftReg_w1_d3_i0\( \+\)/\1AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/ResetCatchAndSync_d3_TestHarness_UNIQUIFIED.sv
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/\( \*\)plusarg_reader\( \+\)/\1plusarg_reader_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/UARTTx_TestHarness_UNIQUIFIED.sv
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/module\( \+\)HellaPeekingArbiter/module\1HellaPeekingArbiter_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/HellaPeekingArbiter_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)HellaPeekingArbiter\( \+\)/\1HellaPeekingArbiter_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TLSerdesser_1.sv
sed -i 's/module\( \+\)GenericSerializer/module\1GenericSerializer_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/GenericSerializer_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)GenericSerializer\( \+\)/\1GenericSerializer_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TLSerdesser_1.sv
sed -i 's/module\( \+\)GenericDeserializer/module\1GenericDeserializer_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/GenericDeserializer_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)GenericDeserializer\( \+\)/\1GenericDeserializer_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TLSerdesser_1.sv
sed -i 's/module\( \+\)Queue_15/module\1Queue_15_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/Queue_15_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)Queue_15\( \+\)/\1Queue_15_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TLBuffer_14.sv
sed -i 's/module\( \+\)Queue_16/module\1Queue_16_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/Queue_16_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)Queue_16\( \+\)/\1Queue_16_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TLBuffer_14.sv
sed -i 's/module\( \+\)AsyncResetSynchronizerPrimitiveShiftReg_d3_i0/module\1AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)AsyncResetSynchronizerPrimitiveShiftReg_d3_i0\( \+\)/\1AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/AsyncResetSynchronizerShiftReg_w1_d3_i0_TestHarness_UNIQUIFIED.sv
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/\( \*\)plusarg_reader\( \+\)/\1plusarg_reader_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TLMonitor_47.sv
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/\( \*\)plusarg_reader\( \+\)/\1plusarg_reader_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/TLMonitor_48.sv
sed -i 's/module\( \+\)plusarg_reader/module\1plusarg_reader_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/plusarg_reader_TestHarness_UNIQUIFIED.v
sed -i 's/module\( \+\)ram_2x80/module\1ram_2x80_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/ram_2x80_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)ram_2x80\( \+\)/\1ram_2x80_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/Queue_15_TestHarness_UNIQUIFIED.sv
sed -i 's/module\( \+\)ram_2x45/module\1ram_2x45_TestHarness_UNIQUIFIED/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/ram_2x45_TestHarness_UNIQUIFIED.sv
sed -i 's/\( \*\)ram_2x45\( \+\)/\1ram_2x45_TestHarness_UNIQUIFIED\2/' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/Queue_16_TestHarness_UNIQUIFIED.sv
sed -e 's;^;/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/;' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/firrtl_black_box_resource_files.f > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.bb.f
sed -i 's/\.\///' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.top.f
sed -i 's/\.\///' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.model.f
sed -i 's/\.\///' /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.bb.f
sort -u /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.top.f /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.model.f /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.bb.f > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.all.f
/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/scripts/split-mems-conf.py \
	--in-smems-conf /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.mems.conf \
	--in-model-hrchy-json /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/model_module_hierarchy.uniquified.json \
	--dut-module-name ChipTop \
	--model-module-name TestHarness \
	--out-dut-smems-conf /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.top.mems.conf \
	--out-model-smems-conf /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.model.mems.conf
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer && java -cp /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.classpath_cache/tapeout.jar barstools.macros.MacroCompiler -n /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.top.mems.conf -v /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/chipyard.harness.TestHarness.TinyRocketConfig.top.mems.v -f /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.top.mems.fir -l  /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/technology/sky130/sram-cache.json -hir /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.mems.hammer.json --mode strict
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.java_tmp
cat /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.top.f | sort -u > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/syn.f
echo /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/chipyard.harness.TestHarness.TinyRocketConfig.top.mems.v >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/syn.f
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/
echo "sim.inputs:" > /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "  input_files:" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
for x in $(cat /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/syn.f); do \
	echo '    - "'$x'"' >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml; \
done
echo "  input_files_meta: 'append'" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "synthesis.inputs:" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "  top_module: ChipTop" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "  input_files:" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
for x in $(cat /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/syn.f); do \
	echo '    - "'$x'"' >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/inputs.yml; \
done
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/
echo "vlsi.inputs.sram_parameters: '/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.mems.hammer.json'" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/sram_generator-input.yml
echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/sram_generator-input.yml
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi &&  ./example-vlsi-sky130 -e /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/env.yml  -p example-openroad.yml  -p example-sky130.yml  -p example-designs/sky130-openroad.yml  -p /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/sram_generator-input.yml --obj_dir /home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig sram_generator
[<global>] Loading hammer-vlsi libraries and reading settings
[<global>] Loading technology 'hammer.technology.sky130'
[<global>] Key technology.sky130.sky130_cds has a type str is not yet implemented
[<global>] Key technology.sky130.openram_lib has a type str is not yet implemented
[<global>] Key technology.sky130.dffram_lib has a type Optional[str] is not yet implemented
[<global>] Key technology.sky130.pdk_home has a type Optional[str] is not yet implemented
[<global>] Key technology.sky130.lvs_deck_sources has a type Optional[list[str]] is not yet implemented
[<global>] Key technology.sky130.io_file has a type str is not yet implemented
[tech] The install path: /path/to/skywater-src-nda does not exist, looked at key technology.sky130.sky130_nda
Traceback (most recent call last):
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/./example-vlsi-sky130", line 63, in <module>
    ExampleDriver().main()
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/vlsi/cli_driver.py", line 1725, in main
    sys.exit(self.run_main_parsed(vars(parser.parse_args(args))))
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/vlsi/cli_driver.py", line 1617, in run_main_parsed
    driver, errors = self.args_to_driver(args)
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/vlsi/cli_driver.py", line 1376, in args_to_driver
    driver = HammerDriver(options, config)
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/vlsi/driver.py", line 104, in __init__
    self.load_technology()
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/vlsi/driver.py", line 166, in load_technology
    tech.extract_technology_files()
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/tech/__init__.py", line 714, in extract_technology_files
    self.post_install_script()
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/technology/sky130/__init__.py", line 30, in post_install_script
    self.setup_cdl()
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/.conda-env/lib/python3.10/site-packages/hammer/technology/sky130/__init__.py", line 45, in setup_cdl
    raise FileNotFoundError(f"CDL not found: {source_path}")
FileNotFoundError: CDL not found: ~/.conda-sky130/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl
make: *** No rule to make target '/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/sram_generator-output.json', needed by '/home/riscv/Documents/618yard/chipyardSrc/chipyard1.11.0/MiaoSuanComputer/vlsi/build-sky130-openroad/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop/hammer.d'.  Stop.

My example-openroad.yml is as following:

synthesis.yosys.yosys_bin: ~/.conda-yosys/bin/yosys
par.openroad.openroad_bin: ~/.conda-openroad/bin/openroad
par.openroad.klayout_bin: ~/.conda-klayout/bin/klayout  # binary that OpenROAD calls for final GDS writeout
drc.klayout.klayout_bin: ~/.conda-klayout/bin/klayout   # binary that runs for DRC step
drc.magic.magic_bin: ~/.conda-signoff/bin/magic
lvs.netgen.netgen_bin: ~/.conda-signoff/bin/netgen

# Tool options. Replace with your tool plugin of choice.
vlsi.core.build_system: make
# Synthesis: Yosys
vlsi.core.synthesis_tool: "hammer.synthesis.yosys"
# Place-and-Route: OpenROAD
vlsi.core.par_tool: "hammer.par.openroad"
# DRC: KLayout or Magic (comment other one out)
vlsi.core.drc_tool: "hammer.drc.klayout"
# vlsi.core.drc_tool: "hammer.drc.magic"
# LVS: Netgen
vlsi.core.lvs_tool: "hammer.lvs.netgen"

My example-sky130.yml is as follows:

technology.sky130.sky130A: ~/.conda-sky130/share/pdk/sky130A
technology.sky130.sram22_sky130_macros: /home/riscv/sram22_sky130_macros
# Technology Setup
# Technology used is Sky130
vlsi.core.technology: "hammer.technology.sky130"

vlsi.core.max_threads: 12

# Technology paths
technology.sky130:
  sky130A: ~/.conda-sky130/share/pdk/sky130A
  sram22_sky130_macros: /home/riscv/sram22_sky130_macros

  # this key is OPTIONAL, no NDA files will be used if it does not point to a valid path
  sky130_nda: "/path/to/skywater-src-nda"

# General Hammer Inputs

# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.power_spec_mode: "auto"
vlsi.inputs.power_spec_type: "cpf"

# Specify clock signals
vlsi.inputs.clocks: [
  {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"}
]

# Generate Make include to aid in flow
vlsi.core.build_system: make


# Placement Constraints
vlsi.inputs.placement_constraints:
  - path: "ChipTop"
    type: toplevel
    x: 0
    y: 0
    width: 4000
    height: 3000
    margins:
      left: 10
      right: 0
      top: 10
      bottom: 10

  # Place SRAM memory instances
    # data cache
  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 50
    orientation: r90
  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
    type: hardmacro
    x: 50
    y: 800
    orientation: r90

  # tag array
  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 1600
    orientation: r90

  # instruction cache
  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 2100
    orientation: r90


# Power Straps
par.power_straps_mode: generate
par.generate_power_straps_method: by_tracks
par.blockage_spacing: 2.0
par.blockage_spacing_top_layer: met3
par.generate_power_straps_options:
  by_tracks:
    strap_layers:
      - met4
      - met5
    pin_layers:
      - met5
    blockage_spacing_met2: 4.0
    blockage_spacing_met4: 2.0
    track_width: 3
    track_width_met5: 1
    track_spacing: 5
    track_start: 10
    track_start_met5: 1
    power_utilization: 0.1
    power_utilization_met4: 0.1
    power_utilization_met5: 0.1


# Pin placement constraints
vlsi.inputs.pin_mode: generated
vlsi.inputs.pin.generate_mode: semi_auto
vlsi.inputs.pin.assignments: [
  {pins: "*", layers: ["met2", "met4"], side: "bottom"}
]


# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"

/home/riscv/sram22_sky130_macros is where I clone git clone the sram marcos, https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros
So, can anyone in the team please shed me some light about this issue?
Also, When I switch to chipyard 1.8.1(which is the version my team is currently using), and follow the instructions of the 1.8.1 doc, (I already install the prequsities following the 1.11.0 doc, the terminal reports another issue:

  Input Reference Frequency: 100.0 MHz
  Output clock subsystem_sbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock subsystem_pbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock subsystem_fbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock subsystem_cbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock implicit_clock, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)

harnessDividerOnlyClockGenerator Frequency Summary
  Input Reference Frequency: 100.0 MHz
  Output clock buildtop_reference_clock, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
[success] Total time: 24 s, completed Jul 12, 2024, 9:46:19 AM
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard && java -jar /home/riscv/Documents/618yard/chipyardSrc/chipyard/generators/rocket-chip/sbt-launch.jar  ";project tapeout; runMain barstools.tapeout.transforms.GenerateTopAndHarness  --allow-unrecognized-annotations --output-file /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v --harness-o /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.v --input-file /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.fir --syn-top ChipTop --harness-top TestHarness --annotation-file /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.anno.json --top-anno-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.anno.json --top-dotf-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/firrtl_black_box_resource_files.top.f --top-fir /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.fir --harness-anno-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.anno.json --harness-dotf-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/firrtl_black_box_resource_files.harness.f --harness-fir /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.fir --infer-rw --repl-seq-mem -c:TestHarness:-o:/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.conf -thconf /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.mems.conf --target-dir /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig --log-level error "
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard/.java_tmp
WARNING: A terminally deprecated method in java.lang.System has been called
WARNING: System::setSecurityManager has been called by sbt.TrapExit$ (file:/home/riscv/.sbt/boot/scala-2.12.14/org.scala-sbt/sbt/1.5.5/run_2.12-1.5.5.jar)
WARNING: Please consider reporting this to the maintainers of sbt.TrapExit$
WARNING: System::setSecurityManager will be removed in a future release
[info] welcome to sbt 1.5.5 (N/A Java 17.0.3-internal)
[info] loading settings for project global-plugins from idea.sbt ...
[info] loading global plugins from /home/riscv/.sbt/1.0/plugins
[info] loading settings for project chipyard-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] loading settings for project rocketConfig from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project constellation from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project boom from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project ibex from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project tapeout from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] resolving key references (36697 settings) ...
[info] set current project to chipyardRoot (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard/)
[info] set current project to tapeout (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard/)
[info] running (fork) barstools.tapeout.transforms.GenerateTopAndHarness --allow-unrecognized-annotations --output-file /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v --harness-o /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.v --input-file /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.fir --syn-top ChipTop --harness-top TestHarness --annotation-file /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.anno.json --top-anno-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.anno.json --top-dotf-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/firrtl_black_box_resource_files.top.f --top-fir /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.fir --harness-anno-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.anno.json --harness-dotf-out /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/firrtl_black_box_resource_files.harness.f --harness-fir /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.fir --infer-rw --repl-seq-mem -c:TestHarness:-o:/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.conf -thconf /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.harness.mems.conf --target-dir /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig --log-level error
[error] Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard/.java_tmp
[info] *****************************************************
[info] the 1111ReplSeqMemAnnotation is ReplSeqMemAnnotation(,/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.conf)
[info] *****************************************************
[success] Total time: 57 s, completed Jul 12, 2024, 9:47:23 AM
touch /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/firrtl_black_box_resource_files.top.f /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/firrtl_black_box_resource_files.harness.f
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard && java -jar /home/riscv/Documents/618yard/chipyardSrc/chipyard/generators/rocket-chip/sbt-launch.jar  ";project tapeout; runMain barstools.macros.MacroCompiler -n /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.conf -v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.v -f /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.fir --mode synflops"
Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard/.java_tmp
WARNING: A terminally deprecated method in java.lang.System has been called
WARNING: System::setSecurityManager has been called by sbt.TrapExit$ (file:/home/riscv/.sbt/boot/scala-2.12.14/org.scala-sbt/sbt/1.5.5/run_2.12-1.5.5.jar)
WARNING: Please consider reporting this to the maintainers of sbt.TrapExit$
WARNING: System::setSecurityManager will be removed in a future release
[info] welcome to sbt 1.5.5 (N/A Java 17.0.3-internal)
[info] loading settings for project global-plugins from idea.sbt ...
[info] loading global plugins from /home/riscv/.sbt/1.0/plugins
[info] loading settings for project chipyard-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] loading settings for project rocketConfig from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project constellation from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project boom from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project ibex from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project tapeout from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/riscv/Documents/618yard/chipyardSrc/chipyard/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] resolving key references (36697 settings) ...
[info] set current project to chipyardRoot (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard/)
[info] set current project to tapeout (in build file:/home/riscv/Documents/618yard/chipyardSrc/chipyard/)
[info] running (fork) barstools.macros.MacroCompiler -n /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.conf -v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.v -f /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.fir --mode synflops
[error] Picked up JAVA_TOOL_OPTIONS: -Xmx8G -Xss8M -Djava.io.tmpdir=/home/riscv/Documents/618yard/chipyardSrc/chipyard/.java_tmp
[info] name dcache_data_arrays_0_ext depth 4096 width 32 ports mrw mask_gran 8 
[info] name icache_tag_array_ext depth 64 width 84 ports mrw mask_gran 21 
[info] name icache_data_arrays_0_ext depth 1024 width 128 ports mrw mask_gran 32 
[info] name l2_tlb_ram_ext depth 1024 width 37 ports rw  
[info] fromString Test
[info] WrappedArray(name dcache_data_arrays_0_ext depth 4096 width 32 ports mrw mask_gran 8 , name icache_tag_array_ext depth 64 width 84 ports mrw mask_gran 21 , name icache_data_arrays_0_ext depth 1024 width 128 ports mrw mask_gran 32 , name l2_tlb_ram_ext depth 1024 width 37 ports rw  )
[info] name dcache_data_arrays_0_ext depth 4096 width 32 ports mrw mask_gran 8 
[info] name icache_tag_array_ext depth 64 width 84 ports mrw mask_gran 21 
[info] name icache_data_arrays_0_ext depth 1024 width 128 ports mrw mask_gran 32 
[info] name l2_tlb_ram_ext depth 1024 width 37 ports rw  
[info] fromString Test
[info] WrappedArray(name dcache_data_arrays_0_ext depth 4096 width 32 ports mrw mask_gran 8 , name icache_tag_array_ext depth 64 width 84 ports mrw mask_gran 21 , name icache_data_arrays_0_ext depth 1024 width 128 ports mrw mask_gran 32 , name l2_tlb_ram_ext depth 1024 width 37 ports rw  )
[success] Total time: 3 s, completed Jul 12, 2024, 9:47:33 AM
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/
echo "sim.inputs:" > /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "  input_files:" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
for x in /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/EICG_wrapper.v; do \
	echo '    - "'$x'"' >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml; \
done
echo "  input_files_meta: 'append'" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "synthesis.inputs:" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "  top_module: ChipTop" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
echo "  input_files:" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml
for x in /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.mems.v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/EICG_wrapper.v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/ClockDividerN.sv /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/IOCell.v /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/plusarg_reader.v; do \
	echo '    - "'$x'"' >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/inputs.yml; \
done
mkdir -p /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/
echo "vlsi.inputs.sram_parameters: '/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.mems.hammer.json'" >> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/sram_generator-input.yml
echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/sram_generator-input.yml
cd /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi &&  ./example-vlsi-sky130 -e /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/env.yml  -p example-openroad.yml  -p example-sky130.yml  -p example-designs/sky130-openroad.yml  -p /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/sram_generator-input.yml --obj_dir /home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig sram_generator
[<global>] Loading hammer-vlsi libraries and reading settings
Traceback (most recent call last):
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/./example-vlsi-sky130", line 64, in <module>
    ExampleDriver().main()
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer-vlsi/hammer_vlsi/cli_driver.py", line 1669, in main
    sys.exit(self.run_main_parsed(vars(parser.parse_args(args))))
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer-vlsi/hammer_vlsi/cli_driver.py", line 1559, in run_main_parsed
    driver, errors = self.args_to_driver(args)
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer-vlsi/hammer_vlsi/cli_driver.py", line 1320, in args_to_driver
    driver = HammerDriver(options, config)
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer-vlsi/hammer_vlsi/driver.py", line 98, in __init__
    self.load_technology()
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer-vlsi/hammer_vlsi/driver.py", line 139, in load_technology
    tech_str = self.database.get_setting("vlsi.core.technology")  # type: str
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer_config/config_src.py", line 771, in get_setting
    if key not in self.get_config():
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer_config/config_src.py", line 728, in get_config
    self.__config_cache = combine_configs(
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer_config/config_src.py", line 986, in combine_configs
    expanded_config_reduce = reduce(update_and_expand_meta, configs, {})  # type: dict
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer_config/config_src.py", line 667, in update_and_expand_meta
    meta_func(newdict, setting, meta_dict[setting],
  File "/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/hammer/src/hammer_config/config_src.py", line 357, in transclude_action
    with open(value, "r") as f:
FileNotFoundError: [Errno 2] No such file or directory: '/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.mems.hammer.json'
make: *** No rule to make target '/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/sram_generator-output.json', needed by '/home/riscv/Documents/618yard/chipyardSrc/chipyard/vlsi/build-sky130-openroad/chipyard.TestHarness.TinyRocketConfig-ChipTop/hammer.d'.  Stop.

Any help is highly appreciated. Thanks

[arunlee77]

as per https://chipyard.readthedocs.io/en/stable/VLSI/Sky130-OpenROAD-Tutorial.html#example-sky130-yml , all paths should be absolute paths.