VLSI flow issue with Sky130 + openroad hammer tutorial

[arunlee77]

Hi,

I am trying to run the tutorial from https://chipyard.readthedocs.io/en/stable/VLSI/Sky130-OpenROAD-Tutorial.html.

At step https://chipyard.readthedocs.io/en/stable/VLSI/Sky130-OpenROAD-Tutorial.html#place-and-route the par seems to be hanging at global_placement with my PC hanging forever at

[par] [Exec ...l/bin/openroad -no_init -log /...] [NesterovSolve] Iter: 320 overflow: 0.532755 HPWL: 2782
[par] [Exec ...l/bin/openroad -no_init -log /...] [NesterovSolve] Iter: 330 overflow: 0.49038 HPWL: 29835
[par] [Exec ...l/bin/openroad -no_init -log /...] [NesterovSolve] Iter: 340 overflow: 0.462043 HPWL: 2909
[par] [Exec ...l/bin/openroad -no_init -log /...] [NesterovSolve] Iter: 350 overflow: 0.419318 HPWL: 2994
[par] [Exec ...l/bin/openroad -no_init -log /...] [NesterovSolve] Iter: 360 overflow: 0.378793 HPWL: 3012
[

After asking around in chipyard and openroad (absolutely ZERO support to find a solution to the issue) i thought of changing the versions of the tools used.

I tried various versions of openroad, but none of it gave any solution. I tried rebuilding yosys, openroad, klayout and tried various versions, but no solution to the issue.

I started running through the hammer documentation and was able to run the https://github.com/ucb-bar/hammer/tree/master/e2e with skly130 and pass design, ensuring that the tools are compatible.

I started replacing the hammer-vlsi and related python scripts from hammer to chipyard, and i could see that there are some changes in the bahavior. now i am stuck at

[par] [Exec ...l/bin/openroad -no_init -log /...] [INFO PPL-0012] I/O nets HPWL: 157124.25 um.
[par] [Exec ...l/bin/openroad -no_init -log /...] (hammer) write_db pre_resize
[par] [Exec ...l/bin/openroad -no_init -log /...] (hammer) exec ln -sfn pre_resize latest
[par] [Exec ...l/bin/openroad -no_init -log /...] (hammer) estimate_parasitics -placement
[par] [Exec ...l/bin/openroad -no_init -log /...] (hammer) buffer_ports
[par] [Exec ...l/bin/openroad -no_init -log /...] [INFO RSZ-0027] Inserted 41 input buffers.
[par] [Exec ...l/bin/openroad -no_init -log /...] [INFO RSZ-0028] Inserted 37 output buffers.
[par] [Exec ...l/bin/openroad -no_init -log /...] (hammer) repair_design
[par] [Exec ...l/bin/openroad -no_init -log /...] [INFO RSZ-0058] Using max wire length 3431um.

which is also the extend i could go by changing the tools versions. The chipyard tutorial seems to be having issues with the tools compatibility. If anyone has a BKC on this could you please share?

I tried to get the chipyard vlsi done under the hammer and started creating the config-design with the ChipTop from chipyard vlsi.

diff --git a/e2e/Makefile b/e2e/Makefile
index 00c370b..46415a6 100644
--- a/e2e/Makefile
+++ b/e2e/Makefile
@@ -3,10 +3,10 @@ vlsi_dir=$(abspath .)


 # minimal flow configuration variables
-design              ?= pass
+design              ?= ChipTop
 pdk                 ?= sky130
-tools               ?= nop
-env                 ?= bwrc
+tools               ?= or
+env                 ?= my

 extra               ?=  # extra configs
 args                ?=  # command-line args (including step flow control)
@@ -45,4 +45,4 @@ $(HAMMER_D_MK):
 -include $(HAMMER_D_MK)

 clean:
-    rm -rf $(OBJ_DIR) hammer-vlsi-*.log
+       rm -rf $(OBJ_DIR) hammer-vlsi-*.log

cat configs-env/my-env.yml

# pdk
technology.sky130.sky130A: /home/robotics/work/hammer/e2e/share/pdk/sky130A
technology.sky130.sram22_sky130_macros: /home/robotics/work/hammer/e2e/sram22_sky130_macros

# tools
synthesis.yosys.yosys_bin: /home/robotics/.conda-yosys/bin/yosys
par.openroad.openroad_bin: /usr/local/bin/openroad
par.openroad.klayout_bin: /home/robotics/work/klayout/build-release/klayout
drc.klayout.klayout_bin: /home/robotics/work/klayout/build-release/klayout
drc.magic.magic_bin: /usr/local/bin/magic
lvs.netgen.netgen_bin: /home/robotics/.conda-signoff/bin/netgen

common.yml

(hammer-vlsi-py3.10) (base) robotics@tmsbuild014:~/work/hammer/e2e$ cat configs-design/ChipTop/common.yml
# Generate Make include to aid in flow
vlsi.core.build_system: make

vlsi.inputs.power_spec_type: "cpf"
vlsi.inputs.power_spec_mode: "auto"

synthesis.inputs:
  top_module: "ChipTop"
  input_files: [
        "/home/robotics/work/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/ALU.sv",
        "/home/robotics/work/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/gen-collateral/AMOALU.sv",

and so on with all the .sv from chipyard

sky130.yml as

(hammer-vlsi-py3.10) (base) robotics@tmsbuild014:~/work/hammer/e2e$ cat configs-design/ChipTop/sky130.yml
# Specify clock signals
vlsi.inputs.clocks: [
  {name: "clock_uncore", period: "50ns", uncertainty: "2ns"}
]

# Placement Constraints
vlsi.inputs.placement_constraints:
  - path: "ChipTop"
    type: toplevel
    x: 0
    y: 0
    width: 4000
    height: 3000
    margins:
      left: 10
      right: 0
      top: 10
      bottom: 10
  - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 50
    orientation: r90
  - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
    type: hardmacro
    x: 50
    y: 800
    orientation: r90

  # tag array
  - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 1600
    orientation: r90

  # instruction cache
  - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 2100
    orientation: r90

vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"
vlsi.inputs.sram_parameters: '/home/robotics/work/chipyard/vlsi/generated-src/chipyard.harness.TestHarness.TinyRocketConfig/chipyard.harness.TestHarness.TinyRocketConfig.mems.hammer.json'
vlsi.inputs.sram_parameters_meta: ["transclude", "json2list"]

(hammer-vlsi-py3.10) (base) robotics@tmsbuild014:~/work/hammer/e2e$

with these changes, i think there is some progress, but i get an error with make syn

356.3. Executing AST frontend in derive mode using pre-parsed AST for module `\plusarg_reader'.
ERROR: Module `\sram22_2048x32m8w8' referenced in module `\rockettile_dcache_data_arrays_0_ext' in cell `\mem_0_0' is not part of the design.
[synthesis] Did not run write_regs
Traceback (most recent call last):
  File "/home/robotics/work/hammer/.venv/bin/hammer-vlsi", line 6, in <module>
    sys.exit(main())
  File "/home/robotics/work/hammer/hammer/shell/hammer_vlsi.py", line 9, in main
    CLIDriver().main()
  File "/home/robotics/work/hammer/hammer/vlsi/cli_driver.py", line 1727, in main
    sys.exit(self.run_main_parsed(vars(parser.parse_args(args))))
  File "/home/robotics/work/hammer/hammer/vlsi/cli_driver.py", line 1632, in run_main_parsed
    output_config = action_func(driver, errors.append)  # type: Optional[dict]
  File "/home/robotics/work/hammer/hammer/vlsi/cli_driver.py", line 567, in action
    success, output = driver.run_synthesis(
  File "/home/robotics/work/hammer/hammer/vlsi/driver.py", line 930, in run_synthesis
    run_succeeded = self.syn_tool.run(hooks_to_use)
  File "/home/robotics/work/hammer/hammer/vlsi/hammer_tool.py", line 118, in run
    return self.fill_outputs()
  File "/home/robotics/work/hammer/hammer/synthesis/yosys/__init__.py", line 91, in fill_outputs
    raise ValueError("Output mapped verilog %s not found" % (mapped_v)) # better error?
ValueError: Output mapped verilog /home/robotics/work/hammer/e2e/build-sky130-or/ChipTop/syn-rundir/ChipTop.mapped.v not found
make: *** [/home/robotics/work/hammer/e2e/build-sky130-or/ChipTop/hammer.d:73: /home/robotics/work/hammer/e2e/build-sky130-or/ChipTop/syn-rundir/syn-output-full.json] Error 1
(hammer-vlsi-py3.10) (base) robotics@tmsbuild014:~/work/hammer/e2e$

i think this has something to do with sram generation.

Could anyone help with how to configure the sram generation for sky130?

Highly appreciated, If anyone can help to get the tutorial in chipyard for sky130+openroad success.

regards
Arun