RISC-V torture for lowRISC Untethered v.02

[betbatesc]

Hi, I'm trying to run a test generated with the tool "torture test generator" in the DefaultConfig-sim verilator simulator. I want to know if verilator is able to generate a "signature" (register state) at the end of the test program execution. The version of lowRISC that I'm using is Untethered v.02 and a version of torture test that has support to privileged architecture version 1.7. In the README of the torture test is clearly specified that it's not possible to torture the RTL simulator, although since this README has not been modified since a long time ago, I'd like to know if there is one way to use this tool with this version of the lowRISC SoC.