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Torture does not currently test that FP instructions write the proper exception/status (fflag) bits.
One possible implementation would be to occasionally write out to the "signature" memory the current fflags and then reset the fflags before continuing (which is later compared against Spike's output).
The text was updated successfully, but these errors were encountered:
Adding a fragment that reads fflags into a register should suffice; bad values will make their way into the signature directly or indirectly. This will also test the hazard resolution logic more aggressively.
Great idea. Perhaps this can be a part of a CSR sequence family. It's a unit that's fairly under-tested, and we'll want to be able to set the probabilities fairly low since it will typical serialize the pipeline. I'd maybe add rdinstret and mscratch (or it is sscratch?) to it as well since they're both interesting and should be in pretty much all RISC-V implementations.
Torture does not currently test that FP instructions write the proper exception/status (fflag) bits.
One possible implementation would be to occasionally write out to the "signature" memory the current fflags and then reset the fflags before continuing (which is later compared against Spike's output).
The text was updated successfully, but these errors were encountered: