diff --git a/Units/parser-verilog.r/systemverilog-assertion.d/expected.tags b/Units/parser-verilog.r/systemverilog-assertion.d/expected.tags index bff7f2e050..7dacb85809 100644 --- a/Units/parser-verilog.r/systemverilog-assertion.d/expected.tags +++ b/Units/parser-verilog.r/systemverilog-assertion.d/expected.tags @@ -49,6 +49,8 @@ sva_svtb input.sv /^module sva_svtb;$/;" m clk input.sv /^ bit clk;$/;" r module:sva_svtb a input.sv /^ logic a, b;$/;" r module:sva_svtb b input.sv /^ logic a, b;$/;" r module:sva_svtb +dut input.sv /^ dut dut (.*);$/;" i module:sva_svtb +tb input.sv /^ tb tb (.*);$/;" i module:sva_svtb m input.sv /^module m (input a, b);$/;" m a input.sv /^module m (input a, b);$/;" p module:m b input.sv /^module m (input a, b);$/;" p module:m diff --git a/Units/parser-verilog.r/systemverilog-checker.d/expected.tags b/Units/parser-verilog.r/systemverilog-checker.d/expected.tags index fe684b26b9..abd6ce4ba5 100644 --- a/Units/parser-verilog.r/systemverilog-checker.d/expected.tags +++ b/Units/parser-verilog.r/systemverilog-checker.d/expected.tags @@ -38,6 +38,7 @@ bus input.sv /^module m(wire [31:0] bus, logic clk);$/;" n module:m clk input.sv /^module m(wire [31:0] bus, logic clk);$/;" n module:m res input.sv /^ logic res, scan;$/;" r module:m scan input.sv /^ logic res, scan;$/;" r module:m +check_bus input.sv /^ mutex check_bus(bus, posedge clk, res);$/;" i module:m c1 input.sv /^checker c1(event clk, logic[7:0] a, b);$/;" H clk input.sv /^checker c1(event clk, logic[7:0] a, b);$/;" p checker:c1 a input.sv /^checker c1(event clk, logic[7:0] a, b);$/;" p checker:c1 @@ -54,7 +55,10 @@ en input.sv /^module m(input logic rst, clk, logic en, logic[7:0] in1, in2,$/;" in1 input.sv /^module m(input logic rst, clk, logic en, logic[7:0] in1, in2,$/;" p module:m in2 input.sv /^module m(input logic rst, clk, logic en, logic[7:0] in1, in2,$/;" p module:m in_array input.sv /^ in_array [20:0]);$/;" p module:m +check_outside input.sv /^ c1 check_outside(posedge clk, in1, in2);$/;" i module:m v1 input.sv /^ automatic logic [7:0] v1=0;$/;" r module:m +check_inside input.sv /^ c1 check_inside(posedge clk, in1, v1);$/;" i module:m +check_loop input.sv /^ c1 check_loop(posedge clk, in1, in_array[v1]);$/;" i module:m counter_model input.sv /^checker counter_model(logic flag);$/;" H flag input.sv /^checker counter_model(logic flag);$/;" p checker:counter_model counter input.sv /^ bit [2:0] counter = '0;$/;" r checker:counter_model diff --git a/Units/parser-verilog.r/systemverilog-net-var.d/expected.tags b/Units/parser-verilog.r/systemverilog-net-var.d/expected.tags index d4c57571da..4131a8e8fc 100644 --- a/Units/parser-verilog.r/systemverilog-net-var.d/expected.tags +++ b/Units/parser-verilog.r/systemverilog-net-var.d/expected.tags @@ -8,8 +8,13 @@ vw input.sv /^ logic vw; \/\/ no initial assignment$/;" r module:net_decl circ input.sv /^ real circ;$/;" r module:net_decl top input.sv /^module top();$/;" m iBus input.sv /^ interconnect [0:1] iBus;$/;" n module:top +l1 input.sv /^ lDriver l1(iBus[0]);$/;" i module:top +r1 input.sv /^ rDriver r1(iBus[1]);$/;" i module:top +m1 input.sv /^ rlMod m1(iBus);$/;" i module:top rlMod input.sv /^module rlMod(input interconnect [0:1] iBus);$/;" m iBus input.sv /^module rlMod(input interconnect [0:1] iBus);$/;" p module:rlMod +l1 input.sv /^ lMod l1(iBus[0]);$/;" i module:rlMod +r1 input.sv /^ rMod r1(iBus[1]);$/;" i module:rlMod Net_declarations input.sv /^module Net_declarations;$/;" m cap1 input.sv /^ trireg (large) logic #(0,0,0) cap1;$/;" n module:Net_declarations addressT input.sv /^ typedef logic [31:0] addressT;$/;" T module:Net_declarations diff --git a/Units/parser-verilog.r/verilog-instance.d/args.ctags b/Units/parser-verilog.r/verilog-instance.d/args.ctags new file mode 100644 index 0000000000..12b19daf95 --- /dev/null +++ b/Units/parser-verilog.r/verilog-instance.d/args.ctags @@ -0,0 +1,2 @@ +--extras=+q +--sort=no diff --git a/Units/parser-verilog.r/verilog-instance.d/expected.tags b/Units/parser-verilog.r/verilog-instance.d/expected.tags new file mode 100644 index 0000000000..73c7fbabe4 --- /dev/null +++ b/Units/parser-verilog.r/verilog-instance.d/expected.tags @@ -0,0 +1,36 @@ +foo input.v /^module foo # (parameter$/;" m +PAR_A input.v /^ PAR_A = 1,$/;" c module:foo +foo.PAR_A input.v /^ PAR_A = 1,$/;" c module:foo +PAR_B input.v /^ PAR_B = 2$/;" c module:foo +foo.PAR_B input.v /^ PAR_B = 2$/;" c module:foo +a input.v /^ input a, b;$/;" p module:foo +foo.a input.v /^ input a, b;$/;" p module:foo +b input.v /^ input a, b;$/;" p module:foo +foo.b input.v /^ input a, b;$/;" p module:foo +top input.v /^module top (\/*AUTOARG*\/$/;" m +a input.v /^ input a; \/\/ To uut3 of foo.v$/;" p module:top +top.a input.v /^ input a; \/\/ To uut3 of foo.v$/;" p module:top +b input.v /^ input b; \/\/ To uut3 of foo.v$/;" p module:top +top.b input.v /^ input b; \/\/ To uut3 of foo.v$/;" p module:top +unused_pin input.v /^ wire unused_pin;$/;" n module:top +top.unused_pin input.v /^ wire unused_pin;$/;" n module:top +uut1 input.v /^ foo uut1 ($/;" i module:top +top.uut1 input.v /^ foo uut1 ($/;" i module:top +uut2 input.v /^ uut2 ($/;" i module:top +top.uut2 input.v /^ uut2 ($/;" i module:top +uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top +top.uut3 input.v /^ foo uut3 (\/*AUTOINST*\/$/;" i module:top +uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top +top.uut4 input.v /^ uut4 (\/*AUTOINST*\/$/;" i module:top +uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top +top.uut5 input.v /^ uut5 (\/*AUTOINST*\/$/;" i module:top +uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top +top.uut6 input.v /^ foo uut6 [10:0]();$/;" i module:top +uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top +top.uut7 input.v /^ foo uut7 [1:0][10:0]();$/;" i module:top +uut8 input.v /^ foo uut8 () ;$/;" i module:top +top.uut8 input.v /^ foo uut8 () ;$/;" i module:top +func_foo input.v /^ function void func_foo(int a);$/;" f module:top +top.func_foo input.v /^ function void func_foo(int a);$/;" f module:top +a input.v /^ function void func_foo(int a);$/;" p function:top.func_foo +top.func_foo.a input.v /^ function void func_foo(int a);$/;" p function:top.func_foo diff --git a/Units/parser-verilog.r/verilog-instance.d/input.v b/Units/parser-verilog.r/verilog-instance.d/input.v new file mode 100644 index 0000000000..e1b3362f07 --- /dev/null +++ b/Units/parser-verilog.r/verilog-instance.d/input.v @@ -0,0 +1,86 @@ +// Include module declaration in a comment + +module foo # (parameter + PAR_A = 1, + PAR_B = 2 + ) + (/*AUTOARG*/ + // Inputs + a, b + ); + input a, b; + +endmodule: foo + +module top (/*AUTOARG*/ + // Inputs + a, b + ); + //begin: AUTOOUTPUTS + /*AUTOOUTPUT*/ + + //begin: AUTOINPUTS + /*AUTOINPUT*/ + // Beginning of automatic inputs (from unused autoinst inputs) + input a; // To uut3 of foo.v + input b; // To uut3 of foo.v + // End of automatics + + //begin: AUTOWIREs + /*AUTOWIRE*/ + + //begin: AUTOREGINPUTs + /*AUTOREGINPUT*/ + + //begin: AUTOREGs + /*AUTOREGINPUT*/ + + //begin: AUTOUNUSEDs + wire unused_pin; + assign unused_pin = |{ + /*AUTOUNUSED*/ + 1'b0} ; + + //begin: AUTOTIEOFFs + /*AUTOTIEOFF*/ + foo uut1 ( + // Inputs + a, + b), + uut2 ( + .a (a), + .b (b)); + foo uut3 (/*AUTOINST*/ + // Inputs + .a (a), + .b (b)) ; + foo #(3, 4) + uut4 (/*AUTOINST*/ + // Inputs + .a (a), + .b (b)); + foo #(.PAR_A (5), + .PAR_B (6)) + uut5 (/*AUTOINST*/ + // Inputs + .a (a), + .b (b)); + foo uut6 [10:0](); + foo uut7 [1:0][10:0](); + foo uut8 () ; + + /*! Function Description + * + * \param + * + * \return + */ + + function void func_foo(int a); + + endfunction : func_foo + + + + +endmodule: top diff --git a/parsers/verilog.c b/parsers/verilog.c index b6dfe3401a..fbd2d01f99 100644 --- a/parsers/verilog.c +++ b/parsers/verilog.c @@ -68,6 +68,7 @@ typedef enum { K_REGISTER, K_TASK, K_BLOCK, + K_INSTANCE, K_ASSERTION, K_CLASS, K_COVERGROUP, @@ -128,7 +129,8 @@ static kindDefinition VerilogKinds [] = { { true, 'p', "port", "ports" }, { true, 'r', "register", "variable data types" }, { true, 't', "task", "tasks" }, - { true, 'b', "block", "blocks (begin, fork)" } + { true, 'b', "block", "blocks (begin, fork)" }, + { true, 'i', "instance", "instances of module" } }; static kindDefinition SystemVerilogKinds [] = { @@ -141,6 +143,7 @@ static kindDefinition SystemVerilogKinds [] = { { true, 'r', "register", "variable data types" }, { true, 't', "task", "tasks" }, { true, 'b', "block", "blocks (begin, fork)" }, + { true, 'i', "instance" "instances of module or interface" }, { true, 'A', "assert", "assertions (assert, assume, cover, restrict)" }, { true, 'C', "class", "classes" }, { true, 'V', "covergroup","covergroups" }, @@ -1625,6 +1628,19 @@ static int tagNameList (tokenInfo* token, int c) if (c == '=') c = skipExpression (c); } + else if (c == '(' || c == '[') // should be instance + { + c = skipDimension(c); // name_of_instance {unpacked_dimension} + c = skipPastMatch ("()"); // list_of_port_connections + + // if without the next "if" clause, get a instance named: `add_t from the following example + // var `add_t(foo) = '0; + if (c == ';' || c == ',') + { + verbose("find instance: %s with kind %s\n", vStringValue (token->name), getNameForKind(K_INSTANCE)); + createTag (token, K_INSTANCE); + } + } c = skipMacro (c); // `ifdef, `else, `endif, etc. (before comma) if (c != ',' || c == EOF) @@ -1635,10 +1651,6 @@ static int tagNameList (tokenInfo* token, int c) kind = K_UNDEFINED; } while (true); - /* skip port list of module instance: foo bar(xx, yy); */ - c = skipWhite (c); - if (c == '(') - c = skipPastMatch ("()"); return c; }