# TODO custom ddr_base, smp core number according to your hardware
set $ddr_base=0x80000000
set $thread_num=2

# define register base address
# TODO if your soc is just single core and without L2 comment this out
set $soc_smp_base=($mirgb_info & 0xFFFFFC00) + 0x40000

# define image load address
set $opensbi_base=$ddr_base + 0x0
set $uboot_base=$ddr_base + 0x200000
set $fdt_base=$ddr_base + 0x8000000
set $kernel_base=$ddr_base + 0x3000000
set $rootfs_base=$ddr_base + 0x8300000

# reset hardware
monitor reset halt
printf "init hardware....\n"

# Enable smp, though ddrsoc have only one core
# TODO If your cpu only have 1 core, comment this out
set *((long*)($soc_smp_base + 0xc))=0xffffffff

# init each cpu core
set $cur_thread=1
while $cur_thread <= $thread_num
   thread $cur_thread
   # mask interrupt
   set $mstatus=$mstatus & (~0x8)
   # Enable L2 cache
   # TODO If your cpu don't have L2 comment below two lines out
   set *((long*)($soc_smp_base + 0xd8))=0x0
   set *((long*)($soc_smp_base + 0x10))=0x1
   # Enable I/D Cache
   set $mcache_ctl=$mcache_ctl  |  0x100C1
   set $cur_thread=$cur_thread + 1
end

# switch hart0
thread 1

# Fill binary image to ddr memory
printf "load image ....\n"
restore opensbi.bin binary $opensbi_base
restore u-boot.bin binary $uboot_base
restore fdt.dtb binary  $fdt_base
restore kernel.bin binary $kernel_base
restore initrd.bin binary $rootfs_base
printf "start run ....\n"
set $pc=$opensbi_base
set $a0=$mhartid
set $a1=$fdt_base
set $a2=0
continue