mkdir -p /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev-dv/corev_rand_debug for (( idx=0; idx < $((0 + 1)); idx++ )); do \ mkdir -p /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/$idx/test_program; \ done cd /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev-dv/corev_rand_debug && \ vmap work ../work QuestaSim vmap 2022.4_3 Lib Mapping Utility 2023.02 Feb 3 2023 vmap work ../work Modifying modelsim.ini cd /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev-dv/corev_rand_debug && \ vsim \ -sv_seed 1 -64 -suppress 7031 -suppress 8858 -suppress 8522 -suppress 8550 -suppress 8549 -permit_unmatched_virtual_intf -sv_lib /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi +DISABLE_OVPSIM -sv_lib /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/lib/dpi_dasm/lib/Linux64/libdpi_dasm -sv_lib /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/verilab/svlib_dpi -batch -do /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/tools/vsim/vsim.tcl \ cv32e40p_instr_gen_tb_top_vopt \ -sv_lib /tools/questa-2022.4.3/questasim/verilog_src/uvm-1.2/src/../../../uvm-1.2/linux_x86_64/uvm_dpi \ +UVM_TESTNAME=cv32e40p_instr_base_test \ +num_of_tests=1 \ -l corev_rand_debug_0_1.log \ +start_idx=0 \ +num_of_tests=1 \ +UVM_TESTNAME=cv32e40p_instr_base_test \ +asm_file_name_opts=corev_rand_debug \ +ldgen_cp_test_path=/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug \ \ +instr_cnt=50000 +num_of_sub_program=0 +directed_instr_0=riscv_int_numeric_corner_stream,4 +no_fence=1 +no_data_page=1 +no_branch_jump=0 +boot_mode=m +no_csr_instr=1 +no_wfi=0 +no_ebreak=0 +no_dret=1 +set_dcsr_ebreak=1 +enable_misaligned_instr=1 +enable_ebreak_in_debug_rom=0 +set_dcsr_ebreak=0 +enable_debug_single_step=0 +gen_debug_section=1 # vsim -sv_seed 1 -64 -suppress 7031 -suppress 8858 -suppress 8522 -suppress 8550 -suppress 8549 -permit_unmatched_virtual_intf -sv_lib /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi "+DISABLE_OVPSIM" -sv_lib /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/lib/dpi_dasm/lib/Linux64/libdpi_dasm -sv_lib /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/verilab/svlib_dpi -batch -do "/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/tools/vsim/vsim.tcl" cv32e40p_instr_gen_tb_top_vopt -sv_lib /tools/questa-2022.4.3/questasim/verilog_src/uvm-1.2/src/../../../uvm-1.2/linux_x86_64/uvm_dpi "+UVM_TESTNAME=cv32e40p_instr_base_test" "+num_of_tests=1" -l corev_rand_debug_0_1.log "+start_idx=0" "+num_of_tests=1" "+UVM_TESTNAME=cv32e40p_instr_base_test" "+asm_file_name_opts=corev_rand_debug" "+ldgen_cp_test_path=/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug" "+instr_cnt=50000" "+num_of_sub_program=0" "+directed_instr_0=riscv_int_numeric_corner_stream,4" "+no_fence=1" "+no_data_page=1" "+no_branch_jump=0" "+boot_mode=m" "+no_csr_instr=1" "+no_wfi=0" "+no_ebreak=0" "+no_dret=1" "+set_dcsr_ebreak=1" "+enable_misaligned_instr=1" "+enable_ebreak_in_debug_rom=0" "+set_dcsr_ebreak=0" "+enable_debug_single_step=0" "+gen_debug_section=1" # Start time: 11:09:27 on Oct 09,2024 # Loading /tmp/devipriya.rajendran@coeserver_dpi_34181/linux_x86_64_gcc-7.4.0/export_tramp.so # // Questa Sim-64 # // Version 2022.4_3 linux_x86_64 Feb 3 2023 # // # // Copyright 1991-2023 Mentor Graphics Corporation # // All Rights Reserved. # // # // QuestaSim and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # ** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled "questa_uvm_pkg" can be found. # This also means that later if you turn on UVM-aware debugging your debug simulations may have # different random seeds from your non-debug simulations. # Loading sv_std.std # Loading work.riscv_signature_pkg(fast) # Loading work.uvm_pkg(fast) # Loading work.riscv_instr_pkg(fast) # Loading work.riscv_instr_test_pkg(fast) # Loading work.corev_instr_test_pkg(fast) # Loading work.cv32e40p_instr_test_pkg(fast) # Loading work.uvm_pkg_sv_unit(fast) # Loading work.cv32e40p_instr_gen_tb_top(fast) # Compiling /tmp/devipriya.rajendran@coeserver_dpi_34181/linux_x86_64_gcc-7.4.0/exportwrapper.c # Loading /tmp/devipriya.rajendran@coeserver_dpi_34181/linux_x86_64_gcc-7.4.0/vsim_auto_compile.so # Loading /tmp/devipriya.rajendran@coeserver_dpi_34181/linux_x86_64_gcc-7.4.0/STUB_SYMS_OF_imperas_CV32.dpi.so # Loading /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/vendor_lib/imperas/imperas_DV_COREV/bin/Linux64/imperas_CV32.dpi.so # Loading /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/lib/dpi_dasm/lib/Linux64/libdpi_dasm.so # Loading /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/verilab/svlib_dpi.so # Loading /tools/questa-2022.4.3/questasim/verilog_src/uvm-1.2/src/../../../uvm-1.2/linux_x86_64/uvm_dpi.so # # do /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/tools/vsim/vsim.tcl # UVM_INFO /tools/questa-2022.4.3/questasim/verilog_src/uvm-1.2/src/base/uvm_root.svh(392) @ 0: reporter [UVM/RELNOTES] # ---------------------------------------------------------------- # UVM-1.2 # (C) 2007-2014 Mentor Graphics Corporation # (C) 2007-2014 Cadence Design Systems, Inc. # (C) 2006-2014 Synopsys, Inc. # (C) 2011-2013 Cypress Semiconductor Corp. # (C) 2013-2014 NVIDIA Corporation # ---------------------------------------------------------------- # # *********** IMPORTANT RELEASE NOTES ************ # # You are using a version of the UVM library that has been compiled # with `UVM_NO_DEPRECATED undefined. # See http://www.eda.org/svdb/view.php?id=3313 for more details. # # You are using a version of the UVM library that has been compiled # with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined. # See http://www.eda.org/svdb/view.php?id=3770 for more details. # # (Specify +UVM_NO_RELNOTES to turn off this notice) # # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LR_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SC_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOSWAP_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOADD_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOAND_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOOR_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOXOR_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMIN_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMAX_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMINU_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMAXU_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LWSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SWSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_ADDI4SPN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_ADDI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_ADDI16SP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LUI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_ADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_NOP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_MV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_ANDI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_XOR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_OR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_AND # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_BEQZ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_BNEZ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SRLI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SRAI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SLLI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_J # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_JAL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_JR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_JALR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_EBREAK # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FLD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FSD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FLDSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FSDSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FLD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMADD_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMSUB_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FNMSUB_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FNMADD_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FADD_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSUB_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMUL_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FDIV_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSQRT_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSGNJ_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSGNJN_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSGNJX_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMIN_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMAX_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_S_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_D_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FEQ_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FLT_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FLE_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCLASS_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_W_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_WU_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_D_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_D_WU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FSW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FLWSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_FSWSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMADD_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMSUB_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FNMSUB_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FNMADD_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FADD_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSUB_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMUL_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FDIV_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSQRT_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSGNJ_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSGNJN_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSGNJX_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMIN_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMAX_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_W_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_WU_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMV_X_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FEQ_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FLT_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FLE_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCLASS_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_S_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_S_WU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMV_W_X # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LH # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LBU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LHU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SH # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLLI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRLI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRA # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRAI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ADDI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering NOP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LUI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AUIPC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering XOR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering XORI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering OR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ORI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AND # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ANDI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLTI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLTU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLTIU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BEQ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BNE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BLT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BGE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BLTU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BGEU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering JAL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering JALR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FENCE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FENCE_I # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SFENCE_VMA # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ECALL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering EBREAK # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering URET # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRET # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MRET # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering DRET # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering WFI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CSRRW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CSRRS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CSRRC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CSRRWI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CSRRSI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CSRRCI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SEXT_B # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SEXT_H # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ANDN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ORN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering XNOR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GORC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GORCI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CMIX # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CMOV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering PACK # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering PACKU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering PACKH # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLO # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRO # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ROL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ROR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBCLR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBSET # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBINV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBEXT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GREV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GREVI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLOI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SROI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering RORI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBCLRI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBSETI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBINVI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBEXTI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSRI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLZ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CTZ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering PCNT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32_B # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32_H # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32C_B # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32C_H # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32C_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLMUL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLMULR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLMULH # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MIN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MAX # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MINU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MAXU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SHFL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering UNSHFL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BDEP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BEXT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BFP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SHFLI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering UNSHFLI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MUL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MULH # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MULHSU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MULHU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering DIV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering DIVU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering REM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering REMU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LR_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SC_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOSWAP_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOADD_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOAND_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOOR_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOXOR_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMIN_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMAX_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMINU_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering AMOMAXU_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BMATOR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BMATXOR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BMATFLIP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CRC32C_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ADDIWU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ADDWU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SUBWU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ADDU_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SUBU_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLZW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CTZW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering PCNTW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLMULW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLMULRW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CLMULHW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SHFLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering UNSHFLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BDEPW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BEXTW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering BFPW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLLIU_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLOW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SROW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ROLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering RORW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBCLRW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBSETW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBINVW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBEXTW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GREVW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLOIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SROIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering RORIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBCLRIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBSETIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SBINVIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GREVIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSRW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FSRIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GORCW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering GORCIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering PACKW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering PACKUW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_ADDIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SUBW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_ADDW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LDSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SDSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMV_X_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FMV_D_X # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_L_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_LU_D # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_D_L # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_D_LU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_L_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_LU_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_S_L # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering FCVT_S_LU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LWU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering LD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SLLIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRLW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRLIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRAW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SRAIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ADDW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering ADDIW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering SUBW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering MULW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering DIVW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering DIVUW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering REMW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering REMUW # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SRLI64 # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SRAI64 # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SLLI64 # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LQ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SQ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_LQSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering C_SQSP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSETVLI # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSETVL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VRSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWADDU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWSUBU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VADC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMADC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSBC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSBC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAND # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VOR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VXOR # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSLL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSRL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSRA # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VNSRL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VNSRA # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSEQ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSNE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSLTU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSLT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSLEU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSLE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSGTU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSGT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMINU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMIN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMAXU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMAX # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMUL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMULH # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMULHU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMULHSU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VDIVU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VDIV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREMU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWMUL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWMULU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWMULSU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMACC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VNMSAC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VNMSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWMACCU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWMACC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWMACCSU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWMACCUS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMERGE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSADDU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSSUBU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAADDU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VASUBU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VASUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSSRL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSSRA # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VNCLIPU # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VNCLIP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFRSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMUL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFDIV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFRDIV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWMUL # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMACC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNMACC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMSAC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNMSAC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNMADD # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNMSUB # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWMACC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWNMACC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWMSAC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWNMSAC # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFSQRT_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMIN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMAX # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFSGNJ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFSGNJN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFSGNJX # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMFEQ # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMFNE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMFLT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMFLE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMFGT # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMFGE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFCLASS_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMERGE # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMV # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFCVT_XU_F_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFCVT_X_F_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFCVT_F_XU_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFCVT_F_X_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWCVT_XU_F_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWCVT_X_F_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWCVT_F_XU_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWCVT_F_X_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWCVT_F_F_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNCVT_XU_F_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNCVT_X_F_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNCVT_F_XU_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNCVT_F_X_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNCVT_F_F_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFNCVT_ROD_F_F_W # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDSUM_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDMAXU_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDMAX_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDMINU_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDMIN_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDAND_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDOR_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VREDXOR_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWREDSUMU_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VWREDSUM_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFREDOSUM_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFREDSUM_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFREDMAX_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWREDOSUM_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFWREDSUM_VS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMAND_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMNAND_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMANDNOT_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMXOR_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMOR_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMNOR_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMORNOT_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMXNOR_MM # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VPOPC_M # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFIRST_M # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSBF_M # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSIF_M # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMSOF_M # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VIOTA_M # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VID_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMV_X_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMV_S_X # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMV_F_S # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VFMV_S_F # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSLIDEUP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSLIDEDOWN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSLIDE1UP # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSLIDE1DOWN # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VRGATHER # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VCOMPRESS # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMV1R_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMV2R_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMV4R_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VMV8R_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLSE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSSE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLXEI_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSXEI_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSUXEI_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLEFF_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLSEGE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSSEGE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLSEGEFF_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLSSEGE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSSSEGE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VLXSEGEI_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSXSEGEI_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VSUXSEGEI_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOSWAPE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOADDE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOXORE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOANDE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOORE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOMINE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOMAXE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOMINUE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering VAMOMAXUE_V # UVM_INFO /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/isa/riscv_instr.sv(101) @ 0: reporter [riscv_instr] Registering CUSTOM_1 # UVM_WARNING @ 0: reporter [MULTTST] Multiple (2) +UVM_TESTNAME arguments provided on the command line. 'cv32e40p_instr_base_test' will be used. Provided list: cv32e40p_instr_base_test, cv32e40p_instr_base_test. # UVM_INFO @ 0 : reporter [RNTST] Running test cv32e40p_instr_base_test... # UVM_INFO @ 0 : riscv_instr_base_test.sv(42) uvm_test_top [uvm_test_top] Create configuration instance # UVM_INFO @ 0 : riscv_instr_gen_config.sv(581) reporter [cfg] Got boot mode option - m # UVM_INFO @ 0 : riscv_instr_gen_config.sv(593) reporter [cfg] riscv_instr_pkg::supported_privileged_mode = 1 # UVM_INFO @ 0 : riscv_pmp_cfg.sv(136) reporter [pmp_cfg] pmp max offset: 0xffffffff # UVM_INFO @ 0 : riscv_pmp_cfg.sv(157) reporter [pmp_cfg] MAX OFFSET: 0xffffffff # ** Warning: (vsim-8630) Infinity results from division operation. # Time: 0 ps Iteration: 10 Process: /uvm_pkg::uvm_phase::m_run_phases/#FORK#2213_7fefec4237b File: /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/vendor_lib/google/riscv-dv/src/riscv_pmp_cfg.sv Line: 170 # UVM_INFO @ 0 : riscv_instr_base_test.sv(44) uvm_test_top [uvm_test_top] Create configuration instance...done # UVM_INFO @ 0 : riscv_vector_cfg.sv(152) reporter [vector_cfg] Checking emul: 0.12 # UVM_INFO @ 0 : riscv_vector_cfg.sv(152) reporter [vector_cfg] Checking emul: 0.25 # UVM_INFO @ 0 : riscv_vector_cfg.sv(152) reporter [vector_cfg] Checking emul: 0.50 # UVM_INFO @ 0 : riscv_vector_cfg.sv(152) reporter [vector_cfg] Checking emul: 1.00 # UVM_INFO @ 0 : riscv_vector_cfg.sv(152) reporter [vector_cfg] Checking emul: 2.00 # UVM_INFO @ 0 : riscv_vector_cfg.sv(152) reporter [vector_cfg] Checking emul: 4.00 # UVM_INFO @ 0 : riscv_vector_cfg.sv(152) reporter [vector_cfg] Checking emul: 8.00 # UVM_INFO @ 0 : riscv_instr_base_test.sv(100) uvm_test_top [uvm_test_top] riscv_instr_gen_config is randomized: # -------------------------------------------------------------------------------- # Name Type Size Value # -------------------------------------------------------------------------------- # cfg cv32e40p_instr_gen_config - @1347 # main_program_instr_cnt integral 32 'hc350 # sub_program_instr_cnt sa(integral) 0 - # debug_program_instr_cnt integral 32 'h73 # data_page_pattern data_pattern_t 2 INCR_VAL # init_privileged_mode privileged_mode_t 2 MACHINE_MODE # reserved_regs array(riscv_reg_t) 4 - # [0] riscv_reg_t 5 S2 # [1] riscv_reg_t 5 S3 # [2] riscv_reg_t 5 S1 # [3] riscv_reg_t 5 S7 # ra riscv_reg_t 5 S6 # sp riscv_reg_t 5 S3 # tp riscv_reg_t 5 S2 # tvec_alignment integral 32 'h8 # no_data_page integral 1 'h1 # no_branch_jump integral 1 'h0 # no_load_store integral 1 'h0 # no_csr_instr integral 1 'h1 # no_ebreak integral 1 'h0 # no_dret integral 1 'h1 # no_fence integral 1 'h1 # no_wfi integral 1 'h0 # fix_sp integral 1 'h0 # enable_unaligned_load_store integral 1 'h0 # illegal_instr_ratio integral 32 'h0 # hint_instr_ratio integral 32 'h0 # boot_mode_opts string 1 m # enable_page_table_exception integral 32 'h0 # no_directed_instr integral 1 'h0 # enable_interrupt integral 1 'h0 # enable_timer_irq integral 1 'h0 # bare_program_mode integral 1 'h0 # enable_illegal_csr_instruction integral 1 'h0 # enable_access_invalid_csr_level integral 1 'h0 # enable_misaligned_instr integral 1 'h1 # enable_dummy_csr_write integral 1 'h0 # randomize_csr integral 1 'h0 # allow_sfence_exception integral 1 'h0 # no_delegation integral 1 'h1 # force_m_delegation integral 1 'h0 # force_s_delegation integral 1 'h0 # support_supervisor_mode integral 1 'h0 # disable_compressed_instr integral 1 'h0 # signature_addr integral 32 'hdeadbeef # num_of_harts integral 32 'h1 # require_signature_addr integral 1 'h0 # gen_debug_section integral 1 'h1 # enable_ebreak_in_debug_rom integral 1 'h0 # set_dcsr_ebreak integral 1 'h1 # num_debug_sub_program integral 32 'h0 # enable_debug_single_step integral 1 'h0 # single_step_iterations integral 32 'ha8b98adc # set_mstatus_tw integral 1 'h0 # set_mstatus_mprv integral 1 'h0 # max_branch_step integral 32 'h14 # max_directed_instr_stream_seq integral 32 'h14 # enable_floating_point integral 1 'h0 # enable_vector_extension integral 1 'h0 # vector_instr_only integral 1 'h0 # enable_b_extension integral 1 'h0 # enable_bitmanip_groups array(b_ext_group_t) 10 - # [0] b_ext_group_t 32 ZBB # [1] b_ext_group_t 32 ZBS # [2] b_ext_group_t 32 ZBP # [3] b_ext_group_t 32 ZBE # [4] b_ext_group_t 32 ZBF # [5] b_ext_group_t 32 ZBC # [6] b_ext_group_t 32 ZBR # [7] b_ext_group_t 32 ZBM # [8] b_ext_group_t 32 ZBT # [9] b_ext_group_t 32 ZB_TMP # use_push_data_section integral 1 'h0 # mtvec_mode mtvec_mode_t 2 VECTORED # knob_zero_fast_intr_handlers integral 1 'h1 # dp riscv_reg_t 5 S7 # scratch_reg riscv_reg_t 5 S1 # enable_fast_interrupt_handler integral 1 'h0 # use_fast_intr_handler integral 32 'h0 # -------------------------------------------------------------------------------- # # IN COREV # UVM_INFO @ 0 : riscv_asm_program_gen.sv(1510) reporter [asm_gen] Adding directed instruction stream:riscv_int_numeric_corner_stream ratio:4/1000 # UVM_INFO @ 0 : corev_instr_base_test.sv(65) uvm_test_top [uvm_test_top] All directed instructions are applied # UVM_INFO @ 0 : riscv_asm_program_gen.sv(767) reporter [asm_gen] Generating privileged mode routing for MACHINE_MODE # UVM_INFO @ 0 : cv32e40p_privileged_common_seq.sv(74) reporter@@privil_seq [privil_seq] mstatus_val: 0x1800 # UVM_INFO @ 0 : riscv_asm_program_gen.sv(1566) reporter [asm_gen] Insert directed instr stream riscv_int_numeric_corner_stream 200/50000 times # UVM_INFO @ 0 : riscv_instr_sequence.sv(77) reporter@@main [main] Start generating 50000 instruction # UVM_INFO @ 0 : riscv_instr_sequence.sv(87) reporter@@main [main] Finishing instruction generation # UVM_INFO @ 0 : riscv_asm_program_gen.sv(300) reporter [asm_gen] Randomizing call stack..done # UVM_INFO @ 0 : riscv_asm_program_gen.sv(114) reporter [asm_gen] Generating callstack...done # UVM_INFO @ 0 : riscv_asm_program_gen.sv(116) reporter [asm_gen] Post-processing main program...done # UVM_INFO @ 0 : riscv_instr_sequence.sv(326) reporter@@main [main] Injecting 0 illegal instructions, ratio 0/100 # UVM_INFO @ 0 : riscv_instr_sequence.sv(339) reporter@@main [main] Injecting 0 HINT instructions, ratio 0/100 # UVM_INFO @ 0 : riscv_asm_program_gen.sv(118) reporter [asm_gen] Generating main program instruction stream...done # UVM_INFO @ 0 : riscv_asm_program_gen.sv(133) reporter [asm_gen] Inserting sub-programs...done # UVM_INFO @ 0 : riscv_asm_program_gen.sv(134) reporter [asm_gen] Main/sub program generation...done # UVM_INFO @ 0 : riscv_asm_program_gen.sv(1595) reporter [asm_gen] Creating debug ROM # UVM_INFO @ 0 : riscv_instr_sequence.sv(77) reporter@@debug_program [debug_program] Start generating 115 instruction # UVM_INFO @ 0 : riscv_instr_sequence.sv(87) reporter@@debug_program [debug_program] Finishing instruction generation # UVM_INFO @ 0 : riscv_asm_program_gen.sv(300) reporter [debug_rom] Randomizing call stack..done # UVM_INFO @ 0 : riscv_instr_sequence.sv(326) reporter@@debug_program [debug_program] Injecting 0 illegal instructions, ratio 0/100 # UVM_INFO @ 0 : riscv_instr_sequence.sv(339) reporter@@debug_program [debug_program] Injecting 0 HINT instructions, ratio 0/100 # UVM_INFO @ 0 : corev_instr_base_test.sv(67) uvm_test_top [uvm_test_top] Generating corev_rand_debug_0.S # UVM_INFO @ 0 : riscv_asm_program_gen.sv(1427) reporter [asm_gen] corev_rand_debug_0.S is generated # UVM_INFO @ 0 : riscv_instr_base_test.sv(72) uvm_test_top [] TEST FAILED # UVM_INFO @ 0 : riscv_instr_base_test.sv(74) uvm_test_top [] TEST GENERATION DONE # UVM_INFO @ 0 : uvm_report_server.svh(847) reporter [UVM/REPORT/SERVER] # --- UVM Report Summary --- # # ** Report counts by severity # UVM_INFO : 538 # UVM_WARNING : 1 # UVM_ERROR : 0 # UVM_FATAL : 0 # ** Report counts by id # [] 2 # [MULTTST] 1 # [RNTST] 1 # [UVM/RELNOTES] 1 # [asm_gen] 11 # [cfg] 2 # [debug_program] 4 # [debug_rom] 1 # [main] 4 # [pmp_cfg] 2 # [privil_seq] 1 # [riscv_instr] 497 # [uvm_test_top] 5 # [vector_cfg] 7 # # ** Note: $finish : /tools/questa-2022.4.3/questasim/verilog_src/uvm-1.2/src/base/uvm_root.svh(517) # Time: 0 ps Iteration: 259 Instance: /cv32e40p_instr_gen_tb_top # End time: 11:09:31 on Oct 09,2024, Elapsed time: 0:00:04 # Errors: 0, Warnings: 1 # Copy out final assembler files to test directory for (( idx=0; idx < $((0 + 1)); idx++ )); do \ cp -f /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/bsp/link_corev-dv.ld /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/$idx/test_program/link.ld; \ cp /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev-dv/corev_rand_debug/corev_rand_debug_$idx.S /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/$idx/test_program; \ done mkdir -p /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program make bsp make[1]: Entering directory '/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt' ******************************************************************************************* * Compiling the BSP ******************************************************************************************* mkdir -p /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/bsp cp /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/bsp/Makefile /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/bsp make -C /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/bsp \ VPATH=/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/bsp \ RISCV=/opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1 \ RISCV_PREFIX=riscv32-unknown-elf- \ RISCV_EXE_PREFIX=/opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1/bin/riscv32-unknown-elf- \ RISCV_MARCH=rv32imc \ RISCV_CC=gcc \ RISCV_CFLAGS="" \ all make[2]: Entering directory '/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/bsp' make[2]: Nothing to be done for 'all'. make[2]: Leaving directory '/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/bsp' make[1]: Leaving directory '/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt' ******************************************************************************************* * Compiling test-program /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/corev_rand_debug_0.elf ******************************************************************************************* /opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1/bin/riscv32-unknown-elf-gcc \ -DNO_PULP \ -Os -g -static -mabi=ilp32 -march=rv32imc -Wall -pedantic \ \ -I ../../tests/asm \ -I /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/bsp \ -o /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/corev_rand_debug_0.elf \ -nostartfiles \ /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/corev_rand_debug_0.S \ -T /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/link.ld \ -L /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program -L /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/bsp \ -lcv-verif /opt/lowrisc/lowrisc-toolchain-rv32imcb-20240206-1/bin/../lib/gcc/riscv32-unknown-elf/10.2.0/../../../../riscv32-unknown-elf/bin/ld: cannot find -lcv-verif collect2: error: ld returned 1 exit status make: *** [/Projects/marmik_project/devipriya.rajendran/final/core-v-verif/mk/Common.mk:490: /Projects/marmik_project/devipriya.rajendran/final/core-v-verif/cv32e40p/sim/uvmt/vsim_results/default/corev_rand_debug/0/test_program/corev_rand_debug_0.elf] Error 1