Wide DVI display controller with PMOD interface
Tested in 1920x1080@120Hz mode with Digilent's Genesys-2 Board. Fpga test based on Will Green's Verilog code This code also avaliable on GitHub: projf project
Hardware design based on TI's SN75DP139RSBR Chip with TMDS Clock Rates up to 340 MHz. Complete set of files for manufacturing are includes
HW - schematic and design files (BOM, Gerbers ...)
HDL - Double link 1920x1080@120Hz mode test design Verilog source files for Genesys-2 Demo Board
