diff --git a/hw/rtl/core/VX_gpr_slice.sv b/hw/rtl/core/VX_gpr_slice.sv deleted file mode 100644 index b036fc555..000000000 --- a/hw/rtl/core/VX_gpr_slice.sv +++ /dev/null @@ -1,286 +0,0 @@ -// Copyright © 2019-2023 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -`include "VX_define.vh" - -module VX_gpr_slice import VX_gpu_pkg::*; #( - parameter CORE_ID = 0, - parameter CACHE_ENABLE = 0 -) ( - input wire clk, - input wire reset, - - VX_writeback_if.slave writeback_if, - VX_scoreboard_if.slave scoreboard_if, - VX_operands_if.master operands_if -); - `UNUSED_PARAM (CORE_ID) - localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + `NR_BITS; - localparam RAM_ADDRW = `LOG2UP(`NUM_REGS * ISSUE_RATIO); - - localparam STATE_IDLE = 2'd0; - localparam STATE_FETCH1 = 2'd1; - localparam STATE_FETCH2 = 2'd2; - localparam STATE_FETCH3 = 2'd3; - localparam STATE_BITS = 2; - - wire [`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data; - reg [`NR_BITS-1:0] gpr_rd_rid, gpr_rd_rid_n; - reg [ISSUE_WIS_W-1:0] gpr_rd_wis, gpr_rd_wis_n; - - reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data [ISSUE_RATIO-1:0]; - reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data_n [ISSUE_RATIO-1:0]; - reg [`NR_BITS-1:0] cache_reg [ISSUE_RATIO-1:0]; - reg [`NR_BITS-1:0] cache_reg_n [ISSUE_RATIO-1:0]; - reg [`NUM_THREADS-1:0] cache_tmask [ISSUE_RATIO-1:0]; - reg [`NUM_THREADS-1:0] cache_tmask_n [ISSUE_RATIO-1:0]; - reg [ISSUE_RATIO-1:0] cache_eop, cache_eop_n; - - reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n; - reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n; - reg [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data, rs3_data_n; - - reg [STATE_BITS-1:0] state, state_n; - reg [`NR_BITS-1:0] rs2, rs2_n; - reg [`NR_BITS-1:0] rs3, rs3_n; - reg rs2_ready, rs2_ready_n; - reg rs3_ready, rs3_ready_n; - reg data_ready, data_ready_n; - - wire stg_valid_in, stg_ready_in; - - wire is_rs1_zero = (scoreboard_if.data.rs1 == 0); - wire is_rs2_zero = (scoreboard_if.data.rs2 == 0); - wire is_rs3_zero = (scoreboard_if.data.rs3 == 0); - - always @(*) begin - state_n = state; - rs2_n = rs2; - rs3_n = rs3; - rs2_ready_n = rs2_ready; - rs3_ready_n = rs3_ready; - rs1_data_n = rs1_data; - rs2_data_n = rs2_data; - rs3_data_n = rs3_data; - cache_data_n = cache_data; - cache_reg_n = cache_reg; - cache_tmask_n= cache_tmask; - cache_eop_n = cache_eop; - gpr_rd_rid_n = gpr_rd_rid; - gpr_rd_wis_n = gpr_rd_wis; - data_ready_n = data_ready; - - case (state) - STATE_IDLE: begin - if (operands_if.valid && operands_if.ready) begin - data_ready_n = 0; - end - if (scoreboard_if.valid && data_ready_n == 0) begin - data_ready_n = 1; - if (is_rs3_zero || (CACHE_ENABLE != 0 && - scoreboard_if.data.rs3 == cache_reg[scoreboard_if.data.wis] && - (scoreboard_if.data.tmask & cache_tmask[scoreboard_if.data.wis]) == scoreboard_if.data.tmask)) begin - rs3_data_n = (is_rs3_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if.data.wis]; - rs3_ready_n = 1; - end else begin - rs3_ready_n = 0; - gpr_rd_rid_n = scoreboard_if.data.rs3; - data_ready_n = 0; - state_n = STATE_FETCH3; - end - if (is_rs2_zero || (CACHE_ENABLE != 0 && - scoreboard_if.data.rs2 == cache_reg[scoreboard_if.data.wis] && - (scoreboard_if.data.tmask & cache_tmask[scoreboard_if.data.wis]) == scoreboard_if.data.tmask)) begin - rs2_data_n = (is_rs2_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if.data.wis]; - rs2_ready_n = 1; - end else begin - rs2_ready_n = 0; - gpr_rd_rid_n = scoreboard_if.data.rs2; - data_ready_n = 0; - state_n = STATE_FETCH2; - end - if (is_rs1_zero || (CACHE_ENABLE != 0 && - scoreboard_if.data.rs1 == cache_reg[scoreboard_if.data.wis] && - (scoreboard_if.data.tmask & cache_tmask[scoreboard_if.data.wis]) == scoreboard_if.data.tmask)) begin - rs1_data_n = (is_rs1_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if.data.wis]; - end else begin - gpr_rd_rid_n = scoreboard_if.data.rs1; - data_ready_n = 0; - state_n = STATE_FETCH1; - end - end - gpr_rd_wis_n = scoreboard_if.data.wis; - rs2_n = scoreboard_if.data.rs2; - rs3_n = scoreboard_if.data.rs3; - end - STATE_FETCH1: begin - rs1_data_n = gpr_rd_data; - if (~rs2_ready) begin - gpr_rd_rid_n = rs2; - state_n = STATE_FETCH2; - end else if (~rs3_ready) begin - gpr_rd_rid_n = rs3; - state_n = STATE_FETCH3; - end else begin - data_ready_n = 1; - state_n = STATE_IDLE; - end - end - STATE_FETCH2: begin - rs2_data_n = gpr_rd_data; - if (~rs3_ready) begin - gpr_rd_rid_n = rs3; - state_n = STATE_FETCH3; - end else begin - data_ready_n = 1; - state_n = STATE_IDLE; - end - end - STATE_FETCH3: begin - rs3_data_n = gpr_rd_data; - data_ready_n = 1; - state_n = STATE_IDLE; - end - endcase - - if (CACHE_ENABLE != 0 && writeback_if.valid) begin - if ((cache_reg[writeback_if.data.wis] == writeback_if.data.rd) - || (cache_eop[writeback_if.data.wis] && writeback_if.data.sop)) begin - for (integer j = 0; j < `NUM_THREADS; ++j) begin - if (writeback_if.data.tmask[j]) begin - cache_data_n[writeback_if.data.wis][j] = writeback_if.data.data[j]; - end - end - cache_reg_n[writeback_if.data.wis] = writeback_if.data.rd; - cache_eop_n[writeback_if.data.wis] = writeback_if.data.eop; - cache_tmask_n[writeback_if.data.wis] = writeback_if.data.sop ? writeback_if.data.tmask : - (cache_tmask_n[writeback_if.data.wis] | writeback_if.data.tmask); - end - end - end - - always @(posedge clk) begin - if (reset) begin - state <= STATE_IDLE; - cache_eop <= {ISSUE_RATIO{1'b1}}; - data_ready <= 0; - end else begin - state <= state_n; - cache_eop <= cache_eop_n; - data_ready <= data_ready_n; - end - gpr_rd_rid <= gpr_rd_rid_n; - gpr_rd_wis <= gpr_rd_wis_n; - rs2_ready <= rs2_ready_n; - rs3_ready <= rs3_ready_n; - rs2 <= rs2_n; - rs3 <= rs3_n; - rs1_data <= rs1_data_n; - rs2_data <= rs2_data_n; - rs3_data <= rs3_data_n; - cache_data <= cache_data_n; - cache_reg <= cache_reg_n; - cache_tmask <= cache_tmask_n; - end - - assign stg_valid_in = scoreboard_if.valid && data_ready; - assign scoreboard_if.ready = stg_ready_in && data_ready; - - VX_toggle_buffer #( - .DATAW (DATAW) - ) toggle_buffer ( - .clk (clk), - .reset (reset), - .valid_in (stg_valid_in), - .data_in ({ - scoreboard_if.data.uuid, - scoreboard_if.data.wis, - scoreboard_if.data.tmask, - scoreboard_if.data.PC, - scoreboard_if.data.wb, - scoreboard_if.data.ex_type, - scoreboard_if.data.op_type, - scoreboard_if.data.op_args, - scoreboard_if.data.rd - }), - .ready_in (stg_ready_in), - .valid_out (operands_if.valid), - .data_out ({ - operands_if.data.uuid, - operands_if.data.wis, - operands_if.data.tmask, - operands_if.data.PC, - operands_if.data.wb, - operands_if.data.ex_type, - operands_if.data.op_type, - operands_if.data.op_args, - operands_if.data.rd - }), - .ready_out (operands_if.ready) - ); - - assign operands_if.data.rs1_data = rs1_data; - assign operands_if.data.rs2_data = rs2_data; - assign operands_if.data.rs3_data = rs3_data; - - // GPR banks - - reg [RAM_ADDRW-1:0] gpr_rd_addr; - wire [RAM_ADDRW-1:0] gpr_wr_addr; - if (ISSUE_WIS != 0) begin - assign gpr_wr_addr = {writeback_if.data.wis, writeback_if.data.rd}; - always @(posedge clk) begin - gpr_rd_addr <= {gpr_rd_wis_n, gpr_rd_rid_n}; - end - end else begin - assign gpr_wr_addr = writeback_if.data.rd; - always @(posedge clk) begin - gpr_rd_addr <= gpr_rd_rid_n; - end - end - -`ifdef GPR_RESET - reg wr_enabled = 0; - always @(posedge clk) begin - if (reset) begin - wr_enabled <= 1; - end - end -`endif - - for (genvar j = 0; j < `NUM_THREADS; ++j) begin - VX_dp_ram #( - .DATAW (`XLEN), - .SIZE (`NUM_REGS * ISSUE_RATIO), - `ifdef GPR_RESET - .INIT_ENABLE (1), - .INIT_VALUE (0), - `endif - .NO_RWCHECK (1) - ) gpr_ram ( - .clk (clk), - .read (1'b1), - `UNUSED_PIN (wren), - `ifdef GPR_RESET - .write (wr_enabled && writeback_if.valid && writeback_if.data.tmask[j]), - `else - .write (writeback_if.valid && writeback_if.data.tmask[j]), - `endif - .waddr (gpr_wr_addr), - .wdata (writeback_if.data.data[j]), - .raddr (gpr_rd_addr), - .rdata (gpr_rd_data[j]) - ); - end - -endmodule diff --git a/hw/rtl/core/VX_pending_instr.sv b/hw/rtl/core/VX_pending_instr.sv deleted file mode 100644 index af87b53e0..000000000 --- a/hw/rtl/core/VX_pending_instr.sv +++ /dev/null @@ -1,79 +0,0 @@ -// Copyright © 2019-2023 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -`include "VX_define.vh" - -module VX_pending_instr #( - parameter CTR_WIDTH = 12, - parameter ALM_EMPTY = 1, - parameter DECR_COUNT = 1 -) ( - input wire clk, - input wire reset, - input wire incr, - input wire [`NW_WIDTH-1:0] incr_wid, - input wire [DECR_COUNT-1:0] decr, - input wire [DECR_COUNT-1:0][`NW_WIDTH-1:0] decr_wid, - input wire [`NW_WIDTH-1:0] alm_empty_wid, - output wire empty, - output wire alm_empty -); - localparam COUNTW = `CLOG2(DECR_COUNT+1); - - reg [`NUM_WARPS-1:0][CTR_WIDTH-1:0] pending_instrs; - reg [`NUM_WARPS-1:0][COUNTW-1:0] decr_cnt; - reg [`NUM_WARPS-1:0][DECR_COUNT-1:0] decr_mask; - reg [`NUM_WARPS-1:0] incr_cnt, incr_cnt_n; - reg [`NUM_WARPS-1:0] alm_empty_r, empty_r; - - always @(*) begin - incr_cnt_n = 0; - decr_mask = 0; - if (incr) begin - incr_cnt_n[incr_wid] = 1; - end - for (integer i = 0; i < DECR_COUNT; ++i) begin - if (decr[i]) begin - decr_mask[decr_wid[i]][i] = 1; - end - end - end - - for (genvar i = 0; i < `NUM_WARPS; ++i) begin - - wire [COUNTW-1:0] decr_cnt_n; - `POP_COUNT(decr_cnt_n, decr_mask[i]); - - wire [CTR_WIDTH-1:0] pending_instrs_n = pending_instrs[i] + CTR_WIDTH'(incr_cnt[i]) - CTR_WIDTH'(decr_cnt[i]); - - always @(posedge clk) begin - if (reset) begin - incr_cnt[i] <= '0; - decr_cnt[i] <= '0; - pending_instrs[i] <= '0; - alm_empty_r[i] <= 0; - empty_r[i] <= 1; - end else begin - incr_cnt[i] <= incr_cnt_n[i]; - decr_cnt[i] <= decr_cnt_n; - pending_instrs[i] <= pending_instrs_n; - alm_empty_r[i] <= (pending_instrs_n == ALM_EMPTY); - empty_r[i] <= (pending_instrs_n == 0); - end - end - end - - assign alm_empty = alm_empty_r[alm_empty_wid]; - assign empty = (& empty_r); - -endmodule diff --git a/hw/rtl/core/VX_trace.vh b/hw/rtl/core/VX_trace.vh deleted file mode 100644 index 5dc4bc304..000000000 --- a/hw/rtl/core/VX_trace.vh +++ /dev/null @@ -1,387 +0,0 @@ -// Copyright © 2019-2023 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -`ifndef VX_TRACE_VH -`define VX_TRACE_VH - -`ifdef SIMULATION - - task trace_ex_type(input int level, input [`EX_BITS-1:0] ex_type); - case (ex_type) - `EX_ALU: `TRACE(level, ("ALU")); - `EX_LSU: `TRACE(level, ("LSU")); - `EX_FPU: `TRACE(level, ("FPU")); - `EX_SFU: `TRACE(level, ("SFU")); - default: `TRACE(level, ("?")); - endcase - endtask - - task trace_ex_op(input int level, - input [`EX_BITS-1:0] ex_type, - input [`INST_OP_BITS-1:0] op_type, - input VX_gpu_pkg::op_args_t op_args - ); - case (ex_type) - `EX_ALU: begin - case (op_args.alu.xtype) - `ALU_TYPE_ARITH: begin - if (op_args.alu.is_w) begin - if (op_args.alu.use_imm) begin - case (`INST_ALU_BITS'(op_type)) - `INST_ALU_ADD: `TRACE(level, ("ADDIW")); - `INST_ALU_SLL: `TRACE(level, ("SLLIW")); - `INST_ALU_SRL: `TRACE(level, ("SRLIW")); - `INST_ALU_SRA: `TRACE(level, ("SRAIW")); - default: `TRACE(level, ("?")); - endcase - end else begin - case (`INST_ALU_BITS'(op_type)) - `INST_ALU_ADD: `TRACE(level, ("ADDW")); - `INST_ALU_SUB: `TRACE(level, ("SUBW")); - `INST_ALU_SLL: `TRACE(level, ("SLLW")); - `INST_ALU_SRL: `TRACE(level, ("SRLW")); - `INST_ALU_SRA: `TRACE(level, ("SRAW")); - default: `TRACE(level, ("?")); - endcase - end - end else begin - if (op_args.alu.use_imm) begin - case (`INST_ALU_BITS'(op_type)) - `INST_ALU_ADD: `TRACE(level, ("ADDI")); - `INST_ALU_SLL: `TRACE(level, ("SLLI")); - `INST_ALU_SRL: `TRACE(level, ("SRLI")); - `INST_ALU_SRA: `TRACE(level, ("SRAI")); - `INST_ALU_SLT: `TRACE(level, ("SLTI")); - `INST_ALU_SLTU: `TRACE(level, ("SLTIU")); - `INST_ALU_XOR: `TRACE(level, ("XORI")); - `INST_ALU_OR: `TRACE(level, ("ORI")); - `INST_ALU_AND: `TRACE(level, ("ANDI")); - `INST_ALU_LUI: `TRACE(level, ("LUI")); - `INST_ALU_AUIPC: `TRACE(level, ("AUIPC")); - default: `TRACE(level, ("?")); - endcase - end else begin - case (`INST_ALU_BITS'(op_type)) - `INST_ALU_ADD: `TRACE(level, ("ADD")); - `INST_ALU_SUB: `TRACE(level, ("SUB")); - `INST_ALU_SLL: `TRACE(level, ("SLL")); - `INST_ALU_SRL: `TRACE(level, ("SRL")); - `INST_ALU_SRA: `TRACE(level, ("SRA")); - `INST_ALU_SLT: `TRACE(level, ("SLT")); - `INST_ALU_SLTU: `TRACE(level, ("SLTU")); - `INST_ALU_XOR: `TRACE(level, ("XOR")); - `INST_ALU_OR: `TRACE(level, ("OR")); - `INST_ALU_AND: `TRACE(level, ("AND")); - `INST_ALU_CZEQ: `TRACE(level, ("CZERO.EQZ")); - `INST_ALU_CZNE: `TRACE(level, ("CZERO.NEZ")); - default: `TRACE(level, ("?")); - endcase - end - end - end - `ALU_TYPE_BRANCH: begin - case (`INST_BR_BITS'(op_type)) - `INST_BR_EQ: `TRACE(level, ("BEQ")); - `INST_BR_NE: `TRACE(level, ("BNE")); - `INST_BR_LT: `TRACE(level, ("BLT")); - `INST_BR_GE: `TRACE(level, ("BGE")); - `INST_BR_LTU: `TRACE(level, ("BLTU")); - `INST_BR_GEU: `TRACE(level, ("BGEU")); - `INST_BR_JAL: `TRACE(level, ("JAL")); - `INST_BR_JALR: `TRACE(level, ("JALR")); - `INST_BR_ECALL: `TRACE(level, ("ECALL")); - `INST_BR_EBREAK:`TRACE(level, ("EBREAK")); - `INST_BR_URET: `TRACE(level, ("URET")); - `INST_BR_SRET: `TRACE(level, ("SRET")); - `INST_BR_MRET: `TRACE(level, ("MRET")); - default: `TRACE(level, ("?")); - endcase - end - `ALU_TYPE_MULDIV: begin - if (op_args.alu.is_w) begin - case (`INST_M_BITS'(op_type)) - `INST_M_MUL: `TRACE(level, ("MULW")); - `INST_M_DIV: `TRACE(level, ("DIVW")); - `INST_M_DIVU: `TRACE(level, ("DIVUW")); - `INST_M_REM: `TRACE(level, ("REMW")); - `INST_M_REMU: `TRACE(level, ("REMUW")); - default: `TRACE(level, ("?")); - endcase - end else begin - case (`INST_M_BITS'(op_type)) - `INST_M_MUL: `TRACE(level, ("MUL")); - `INST_M_MULH: `TRACE(level, ("MULH")); - `INST_M_MULHSU:`TRACE(level, ("MULHSU")); - `INST_M_MULHU: `TRACE(level, ("MULHU")); - `INST_M_DIV: `TRACE(level, ("DIV")); - `INST_M_DIVU: `TRACE(level, ("DIVU")); - `INST_M_REM: `TRACE(level, ("REM")); - `INST_M_REMU: `TRACE(level, ("REMU")); - default: `TRACE(level, ("?")); - endcase - end - end - default: `TRACE(level, ("?")); - endcase - end - `EX_LSU: begin - if (op_args.lsu.is_float) begin - case (`INST_LSU_BITS'(op_type)) - `INST_LSU_LW: `TRACE(level, ("FLW")); - `INST_LSU_LD: `TRACE(level, ("FLD")); - `INST_LSU_SW: `TRACE(level, ("FSW")); - `INST_LSU_SD: `TRACE(level, ("FSD")); - default: `TRACE(level, ("?")); - endcase - end else begin - case (`INST_LSU_BITS'(op_type)) - `INST_LSU_LB: `TRACE(level, ("LB")); - `INST_LSU_LH: `TRACE(level, ("LH")); - `INST_LSU_LW: `TRACE(level, ("LW")); - `INST_LSU_LD: `TRACE(level, ("LD")); - `INST_LSU_LBU:`TRACE(level, ("LBU")); - `INST_LSU_LHU:`TRACE(level, ("LHU")); - `INST_LSU_LWU:`TRACE(level, ("LWU")); - `INST_LSU_SB: `TRACE(level, ("SB")); - `INST_LSU_SH: `TRACE(level, ("SH")); - `INST_LSU_SW: `TRACE(level, ("SW")); - `INST_LSU_SD: `TRACE(level, ("SD")); - `INST_LSU_FENCE:`TRACE(level,("FENCE")); - default: `TRACE(level, ("?")); - endcase - end - end - `EX_FPU: begin - case (`INST_FPU_BITS'(op_type)) - `INST_FPU_ADD: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FADD.D")); - else - `TRACE(level, ("FADD.S")); - end - `INST_FPU_SUB: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FSUB.D")); - else - `TRACE(level, ("FSUB.S")); - end - `INST_FPU_MUL: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FMUL.D")); - else - `TRACE(level, ("FMUL.S")); - end - `INST_FPU_DIV: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FDIV.D")); - else - `TRACE(level, ("FDIV.S")); - end - `INST_FPU_SQRT: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FSQRT.D")); - else - `TRACE(level, ("FSQRT.S")); - end - `INST_FPU_MADD: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FMADD.D")); - else - `TRACE(level, ("FMADD.S")); - end - `INST_FPU_MSUB: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FMSUB.D")); - else - `TRACE(level, ("FMSUB.S")); - end - `INST_FPU_NMADD: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FNMADD.D")); - else - `TRACE(level, ("FNMADD.S")); - end - `INST_FPU_NMSUB: begin - if (op_args.fpu.fmt[0]) - `TRACE(level, ("FNMSUB.D")); - else - `TRACE(level, ("FNMSUB.S")); - end - `INST_FPU_CMP: begin - if (op_args.fpu.fmt[0]) begin - case (op_args.fpu.frm[1:0]) - 0: `TRACE(level, ("FLE.D")); - 1: `TRACE(level, ("FLT.D")); - 2: `TRACE(level, ("FEQ.D")); - default: `TRACE(level, ("?")); - endcase - end else begin - case (op_args.fpu.frm[1:0]) - 0: `TRACE(level, ("FLE.S")); - 1: `TRACE(level, ("FLT.S")); - 2: `TRACE(level, ("FEQ.S")); - default: `TRACE(level, ("?")); - endcase - end - end - `INST_FPU_F2F: begin - if (op_args.fpu.fmt[0]) begin - `TRACE(level, ("FCVT.D.S")); - end else begin - `TRACE(level, ("FCVT.S.D")); - end - end - `INST_FPU_F2I: begin - if (op_args.fpu.fmt[0]) begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.L.D")); - end else begin - `TRACE(level, ("FCVT.W.D")); - end - end else begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.L.S")); - end else begin - `TRACE(level, ("FCVT.W.S")); - end - end - end - `INST_FPU_F2U: begin - if (op_args.fpu.fmt[0]) begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.LU.D")); - end else begin - `TRACE(level, ("FCVT.WU.D")); - end - end else begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.LU.S")); - end else begin - `TRACE(level, ("FCVT.WU.S")); - end - end - end - `INST_FPU_I2F: begin - if (op_args.fpu.fmt[0]) begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.D.L")); - end else begin - `TRACE(level, ("FCVT.D.W")); - end - end else begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.S.L")); - end else begin - `TRACE(level, ("FCVT.S.W")); - end - end - end - `INST_FPU_U2F: begin - if (op_args.fpu.fmt[0]) begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.D.LU")); - end else begin - `TRACE(level, ("FCVT.D.WU")); - end - end else begin - if (op_args.fpu.fmt[1]) begin - `TRACE(level, ("FCVT.S.LU")); - end else begin - `TRACE(level, ("FCVT.S.WU")); - end - end - end - `INST_FPU_MISC: begin - if (op_args.fpu.fmt[0]) begin - case (op_args.fpu.frm) - 0: `TRACE(level, ("FSGNJ.D")); - 1: `TRACE(level, ("FSGNJN.D")); - 2: `TRACE(level, ("FSGNJX.D")); - 3: `TRACE(level, ("FCLASS.D")); - 4: `TRACE(level, ("FMV.X.D")); - 5: `TRACE(level, ("FMV.D.X")); - 6: `TRACE(level, ("FMIN.D")); - 7: `TRACE(level, ("FMAX.D")); - endcase - end else begin - case (op_args.fpu.frm) - 0: `TRACE(level, ("FSGNJ.S")); - 1: `TRACE(level, ("FSGNJN.S")); - 2: `TRACE(level, ("FSGNJX.S")); - 3: `TRACE(level, ("FCLASS.S")); - 4: `TRACE(level, ("FMV.X.S")); - 5: `TRACE(level, ("FMV.S.X")); - 6: `TRACE(level, ("FMIN.S")); - 7: `TRACE(level, ("FMAX.S")); - endcase - end - end - default: `TRACE(level, ("?")); - endcase - end - `EX_SFU: begin - case (`INST_SFU_BITS'(op_type)) - `INST_SFU_TMC: `TRACE(level, ("TMC")); - `INST_SFU_WSPAWN:`TRACE(level, ("WSPAWN")); - `INST_SFU_SPLIT: begin if (op_args.wctl.is_neg) `TRACE(level, ("SPLIT.N")); else `TRACE(level, ("SPLIT")); end - `INST_SFU_JOIN: `TRACE(level, ("JOIN")); - `INST_SFU_BAR: `TRACE(level, ("BAR")); - `INST_SFU_PRED: begin if (op_args.wctl.is_neg) `TRACE(level, ("PRED.N")); else `TRACE(level, ("PRED")); end - `INST_SFU_CSRRW: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRWI")); else `TRACE(level, ("CSRRW")); end - `INST_SFU_CSRRS: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRSI")); else `TRACE(level, ("CSRRS")); end - `INST_SFU_CSRRC: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRCI")); else `TRACE(level, ("CSRRC")); end - default: `TRACE(level, ("?")); - endcase - end - default: `TRACE(level, ("?")); - endcase - endtask - - task trace_op_args(input int level, - input [`EX_BITS-1:0] ex_type, - input [`INST_OP_BITS-1:0] op_type, - input VX_gpu_pkg::op_args_t op_args - ); - case (ex_type) - `EX_ALU: begin - `TRACE(level, (", use_PC=%b, use_imm=%b, imm=0x%0h", op_args.alu.use_PC, op_args.alu.use_imm, op_args.alu.imm)); - end - `EX_LSU: begin - `TRACE(level, (", offset=0x%0h", op_args.lsu.offset)); - end - `EX_FPU: begin - `TRACE(level, (", fmt=0x%0h, frm=0x%0h", op_args.fpu.fmt, op_args.fpu.frm)); - end - `EX_SFU: begin - if (`INST_SFU_IS_CSR(op_type)) begin - `TRACE(level, (", addr=0x%0h, use_imm=%b, imm=0x%0h", op_args.csr.addr, op_args.csr.use_imm, op_args.csr.imm)); - end - end - default:; - endcase - endtask - - task trace_base_dcr(input int level, input [`VX_DCR_ADDR_WIDTH-1:0] addr); - case (addr) - `VX_DCR_BASE_STARTUP_ADDR0: `TRACE(level, ("STARTUP_ADDR0")); - `VX_DCR_BASE_STARTUP_ADDR1: `TRACE(level, ("STARTUP_ADDR1")); - `VX_DCR_BASE_STARTUP_ARG0: `TRACE(level, ("STARTUP_ARG0")); - `VX_DCR_BASE_STARTUP_ARG1: `TRACE(level, ("STARTUP_ARG1")); - `VX_DCR_BASE_MPM_CLASS: `TRACE(level, ("MPM_CLASS")); - default: `TRACE(level, ("?")); - endcase - endtask - -`endif - -`endif // VX_TRACE_VH