diff --git a/hw/rtl/libs/VX_stream_buffer.sv b/hw/rtl/libs/VX_stream_buffer.sv
index 2cf08c0f4..ea4467cb3 100644
--- a/hw/rtl/libs/VX_stream_buffer.sv
+++ b/hw/rtl/libs/VX_stream_buffer.sv
@@ -12,7 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-// A stream elastic buffer operates at full-bandwidth where fire_in and fire_out can happen simultaneously
+// A stream elastic buffer_r operates at full-bandwidth where fire_in and fire_out can happen simultaneously
 // It has the following benefits:
 // + full-bandwidth throughput
 // + ready_in and ready_out are decoupled
@@ -45,88 +45,66 @@ module VX_stream_buffer #(
         assign valid_out = valid_in;
         assign data_out  = data_in;
 
-	end else if (OUT_REG != 0) begin : g_out_reg
+	end else begin : g_buffer
 
-		reg [DATAW-1:0] data_out_r;
-		reg [DATAW-1:0] buffer;
-		reg             valid_out_r;
-		reg             no_buffer;
+		reg [DATAW-1:0] data_out_r, buffer_r;
+		reg valid_out_r, valid_in_r;
 
 		wire fire_in = valid_in && ready_in;
 		wire flow_out = ready_out || ~valid_out;
 
 		always @(posedge clk) begin
 			if (reset) begin
-				valid_out_r <= 0;
-				no_buffer  <= 1;
-			end else begin
-				if (flow_out) begin
-					no_buffer <= 1;
-				end else if (valid_in) begin
-					no_buffer <= 0;
-				end
-				if (flow_out) begin
-					valid_out_r <= valid_in || ~no_buffer;
-				end
+				valid_in_r <= 1'b1;
+			end else if (valid_in || flow_out) begin
+				valid_in_r <= flow_out;
 			end
 		end
 
 		always @(posedge clk) begin
-			if (fire_in) begin
-				buffer <= data_in;
-			end
-			if (flow_out) begin
-				data_out_r <= no_buffer ? data_in : buffer;
+			if (reset) begin
+				valid_out_r <= 1'b0;
+			end else if (flow_out) begin
+				valid_out_r <= valid_in || ~valid_in_r;
 			end
 		end
 
-		assign ready_in  = no_buffer;
-		assign valid_out = valid_out_r;
-		assign data_out  = data_out_r;
+		if (OUT_REG != 0) begin : g_out_reg
 
-	end else begin : g_no_out_reg
+			always @(posedge clk) begin
+				if (fire_in) begin
+					buffer_r <= data_in;
+				end
+			end
 
-		reg [DATAW-1:0] data_out_r, buffer;
-		reg valid_in_r, valid_out_r;
+			always @(posedge clk) begin
+				if (flow_out) begin
+					data_out_r <= valid_in_r ? data_in : buffer_r;
+				end
+			end
 
-		wire fire_in = valid_in && ready_in;
-		wire fire_out = valid_out && ready_out;
+			assign data_out = data_out_r;
 
-		always @(posedge clk) begin
-			if (reset) begin
-				valid_in_r  <= 1'b1;
-			end else begin
-				if (fire_in ^ fire_out) begin
-					valid_in_r  <= valid_out_r ^ fire_in;
+		end else begin : g_no_out_reg
+
+			always @(posedge clk) begin
+				if (fire_in) begin
+					data_out_r <= data_in;
 				end
 			end
-		end
 
-		always @(posedge clk) begin
-			if (reset) begin
-				valid_out_r <= 1'b0;
-			end else begin
-				if (fire_in ^ fire_out) begin
-					valid_out_r <= valid_in_r ^ fire_out;
+			always @(posedge clk) begin
+				if (fire_in) begin
+					buffer_r <= data_out_r;
 				end
 			end
-		end
 
-		always @(posedge clk) begin
-			if (fire_in) begin
-				data_out_r <= data_in;
-			end
-		end
+			assign data_out  = valid_in_r ? data_out_r : buffer_r;
 
-		always @(posedge clk) begin
-			if (fire_in) begin
-				buffer <= data_out_r;
-			end
 		end
 
-		assign ready_in  = valid_in_r;
 		assign valid_out = valid_out_r;
-		assign data_out  = valid_in_r ? data_out_r : buffer;
+		assign ready_in  = valid_in_r;
 
 	end