how to understand the fpga setup guide?

[michaelw2022]

in this guide, it seems we need to use XSA file to create vitis platform firstly, which is .xpfm file, so the command platforminfo -l can find the platform, in the third commad: PREFIX=test1 PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 TARGET=hw NUM_CORES=4 make, it will use the source file such as hw/rtl/ to generate bitstream.
my question is that, When I use Vivado to generate the XSA file, these RTL source files have already been used and the bitstream has been generated simultaneously. Is this step redundant?

[Udit8348]

Yes your understanding is correct, the issue is that you are reading the steps for both Xilinx and Intel FGPA synthesis. Like you mentioned you have to run make to generate a bitstream and then you can run that bitstream on the FPGA.

It seems like you are looking at an older (incomplete) version of the docs. You can refer to the docs on master here. These have the complete and correct steps, which should make more sense.