- This is the FPGA clahe code written in Vivado HLS.
- We use Vivado 2019.1 and Vivado HLS 2019.1.
- target board is PYNQ Z1.
- target frequency is 111 MHz for 1920x1080 and 125 MHz for 512x512.
- the source code is in .setting dirctory.
-
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weikaijie1994/fpga_clahe
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