diff --git a/boards/phytec/phyboard_nash/Kconfig.phyboard_nash b/boards/phytec/phyboard_nash/Kconfig.phyboard_nash new file mode 100644 index 00000000000000..4640f4aaee03ea --- /dev/null +++ b/boards/phytec/phyboard_nash/Kconfig.phyboard_nash @@ -0,0 +1,7 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_NASH + select SOC_MIMX9352_A55 if BOARD_PHYBOARD_NASH_MIMX9352_A55 + select SOC_MIMX9352_M33 if BOARD_PHYBOARD_NASH_MIMX9352_M33 + select SOC_PART_NUMBER_MIMX9352CVVXM diff --git a/boards/phytec/phyboard_nash/board.cmake b/boards/phytec/phyboard_nash/board.cmake new file mode 100644 index 00000000000000..37a788d10d847d --- /dev/null +++ b/boards/phytec/phyboard_nash/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024, PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +board_set_debugger_ifnset(jlink) +board_set_flasher_ifnset(jlink) + +board_runner_args(jlink "--device=MIMX9352_M33") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/phytec/phyboard_nash/board.yml b/boards/phytec/phyboard_nash/board.yml new file mode 100644 index 00000000000000..e64828c1309e6e --- /dev/null +++ b/boards/phytec/phyboard_nash/board.yml @@ -0,0 +1,5 @@ +board: + name: phyboard_nash + vendor: phytec + socs: + - name: mimx9352 diff --git a/boards/phytec/phyboard_nash/doc/img/phyboard_nash.webp b/boards/phytec/phyboard_nash/doc/img/phyboard_nash.webp new file mode 100644 index 00000000000000..05d4e30c56a8f8 Binary files /dev/null and b/boards/phytec/phyboard_nash/doc/img/phyboard_nash.webp differ diff --git a/boards/phytec/phyboard_nash/doc/index.rst b/boards/phytec/phyboard_nash/doc/index.rst new file mode 100644 index 00000000000000..16c281e9962971 --- /dev/null +++ b/boards/phytec/phyboard_nash/doc/index.rst @@ -0,0 +1,178 @@ +.. _phyboard_nash: + +phyBOARD-Nash i.MX93 +#################### + +Overview +******** + +The phyBOARD-Nash is based on the phyCORE-i.MX93 SoM is based on the NXP i.MX93 +SoC. It features common industrial interfaces and can be used as a reference for +development or in the final product. It is an entry-level development board, +which helps developers to get familiar with the module before investing a large +amount of resources in more specific designs. + +i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single +Cortex-M33 core. Zephyr OS is ported to run on one of the Cortex-A55 core as +well as the Cortex-M33 core. + +- Memory: + + - RAM: 512 MB - 2GB LPDDR4 + - EEPROM: 4 kB - 32 kB + - eMMC: 8 GB - 256 GB + +- Interfaces: + + - Ethernet: 2x 10/100BASE-T (1x TSN Support) + - USB: 2x 2.0 Host / OTG + - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex + - CAN: 1x CAN FD + - Digital I/O: via Expansion Connector + - MMX/SD/SDIO: microSD slot + - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI + - Audio: SAI + - Camera: 1x MIPI CSI-2 (phyCAM-M), 1x Parallel + - Expansion Bus: I2C, SPI, SDIO, UART, USB + +- Debug: + + - JTAG 10-pin connector + - USB-C for UART debug, 2x serial ports for A55 and M33 + + +.. image:: img/phyboard_nash.webp + :width: 720px + :align: center + :height: 405px + :alt: phyBOARD-Nash + +More information about the board can be found at the `PHYTEC website`_. + +Supported Features +================== + +The ``phyboard_nash/mimx9352/a55`` board target supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v4 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | TPM Counter | ++-----------+------------+-------------------------------------+ + +The ``phyboard_nash/mimx9352/m33`` board target supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. Cortex-A55 +Core runs up to 1.7 GHz. Cortex-M33 Core runs up to 200MHz in which SYSTICK runs +on same frequency. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART2 for A55 core and M33 core. The u-boot bootloader or Linux use the +second serial port for debug output. + +Programming and Debugging (A55) +******************************* + +Copy the compiled ``zephyr.bin`` to the ``BOOT`` partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and execute zephyr.bin on Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_nash/mimx9352/a55 + :goals: build + +Use this configuration to run basic Zephyr applications, for example: + +.. code-block:: console + + *** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d *** + Hello World! phyboard_nash/mimx9352/a55 + +Programming and Debugging (M33) +******************************* + +Copy the compiled ``zephyr.bin`` to the ``BOOT`` partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core: + +.. code-block:: console + + load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0 + +Use this configuration to run basic Zephyr applications, for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_nash/mimx9352/m33 + :goals: build + +This will build an image with the synchronization sample app, boot it and +display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d *** + Hello World! phyboard_nash/mimx9352/m33 + +Starting the M7-Core from U-Boot and Linux +========================================== + +Loading binaries and starting the M33-Core is supported from Linux via +remoteproc. Please check the `phyCORE-i.MX93 BSP Manual`_ for more information. + +References +========== + +For more information refer to the `PHYTEC website`_. + +.. _PHYTEC website: + https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ +.. _phyCORE-i.MX93 BSP Manual: + https://phytec.github.io/doc-bsp-yocto/bsp/imx9/imx93/imx93.html diff --git a/boards/phytec/phyboard_nash/phyboard_nash-pinctrl.dtsi b/boards/phytec/phyboard_nash/phyboard_nash-pinctrl.dtsi new file mode 100644 index 00000000000000..b9bfda29c04e3f --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright 2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart2_default: uart2_default { + group0 { + pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>, + <&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; +}; diff --git a/boards/phytec/phyboard_nash/phyboard_nash_a55.dts b/boards/phytec/phyboard_nash/phyboard_nash_a55.dts new file mode 100644 index 00000000000000..0c6c67ad7ac78a --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_a55.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2022,2024 NXP + * Copyright 2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_nash-pinctrl.dtsi" + +/ { + model = "PHYTEC phyBOARD-Nash i.MX93"; + compatible = "phytec,phyboard_nash"; + + chosen { + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + sram0: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/phytec/phyboard_nash/phyboard_nash_a55.yaml b/boards/phytec/phyboard_nash/phyboard_nash_a55.yaml new file mode 100644 index 00000000000000..b48692ee9e7104 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_a55.yaml @@ -0,0 +1,18 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +identifier: phyboard_nash/mimx9352/a55 +name: PHYTEC phyBOARD-Nash i.MX93 A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth +vendor: phytec diff --git a/boards/phytec/phyboard_nash/phyboard_nash_a55_defconfig b/boards/phytec/phyboard_nash/phyboard_nash_a55_defconfig new file mode 100644 index 00000000000000..c714bcaac772b9 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_a55_defconfig @@ -0,0 +1,24 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y diff --git a/boards/phytec/phyboard_nash/phyboard_nash_m33.dts b/boards/phytec/phyboard_nash/phyboard_nash_m33.dts new file mode 100644 index 00000000000000..e1fcbe244b0140 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_m33.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_nash-pinctrl.dtsi" + +/ { + model = "PHYTEC phyBOARD-Nash i.MX93"; + compatible = "phytec,phyboard_nash"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/phytec/phyboard_nash/phyboard_nash_m33.yaml b/boards/phytec/phyboard_nash/phyboard_nash_m33.yaml new file mode 100644 index 00000000000000..3927ba8d1dbcb1 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_m33.yaml @@ -0,0 +1,15 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +identifier: phyboard_nash/mimx9352/m33 +name: PHYTEC phyBOARD Nash (i.MX93) M33 +type: mcu +arch: arm +toolchain: + - zephyr + - cross-compile +ram: 128 +flash: 128 +supported: + - uart +vendor: phytec diff --git a/boards/phytec/phyboard_nash/phyboard_nash_m33_defconfig b/boards/phytec/phyboard_nash/phyboard_nash_m33_defconfig new file mode 100644 index 00000000000000..5538854b5995a2 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_m33_defconfig @@ -0,0 +1,9 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y