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Releases: zeroasiccorp/switchboard

v0.0.41

16 Apr 19:12
cecce1d
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switchboard 0.0.41 (2024-04-16)

Minor:

  • AXI bug fixes #211

v0.0.40

15 Apr 15:04
1e1795c
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switchboard 0.0.40 (2024-04-15)

Major:

  • Full AXI driver #208

v0.0.39

04 Apr 18:29
3815290
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switchboard 0.0.39 (2024-04-04)

Major:

  • First-pass AXI-Lite interface #204

v0.0.38

07 Mar 23:54
aba8774
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switchboard 0.0.38 (2024-03-07)

Major:

  • Easy-to-use AMS simulation interface, where SPICE subcircuits can be instantiated in Verilog code as ordinary Verilog modules. Analog/digital interfaces are configured using the SbDut.input_analog() method.

v0.0.37

15 Feb 23:11
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switchboard 0.0.37 (2024-02-15)

Minor:

  • By default, check for the BLKSEQ warning when running a Verilator build. This behavior can be disabled by setting warnings=[] when instantiating SbDut.

v0.0.36

07 Feb 19:16
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switchboard 0.0.36 (2024-02-07)

Minor:

  • By default, error out with a traceback when there are issues with UMI responses. Errors can be demoted to warnings by setting error=False in the UmiTxRx constructor or on a transaction-by-transaction basis.

v0.0.35

26 Jan 18:08
d830c33
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switchboard 0.0.35 (2024-01-26)

Minor:

  • Allow instantiations of end caps with different DW values

v0.0.34

22 Jan 18:57
95af770
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switchboard 0.0.34 (2024-01-22)

Minor:

  • Fix args argument to SbDut.simulate()

v0.0.33

18 Jan 20:15
9b06045
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switchboard 0.0.33 (2024-01-18)

Major:

  • Experimental support for Xyce co-simulation

v0.0.32

07 Dec 20:31
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switchboard 0.0.32 (2023-12-07)

Minor:

  • Automatically publish to PyPI upon GitHub publication of a new release