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cpu.c
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#include <stdio.h>
#include "mem.h"
#include "rom.h"
#include "interrupt.h"
#include "timer.h"
#define set_HL(x) do {unsigned int macro = (x); c.L = macro&0xFF; c.H = macro>>8;} while(0)
#define set_BC(x) do {unsigned int macro = (x); c.C = macro&0xFF; c.B = macro>>8;} while(0)
#define set_DE(x) do {unsigned int macro = (x); c.E = macro&0xFF; c.D = macro>>8;} while(0)
#define set_AF(x) do {unsigned int macro = (x); c.F = macro&0xFF; c.A = macro>>8;} while(0)
#define get_AF() ((c.A<<8) | c.F)
#define get_BC() ((c.B<<8) | c.C)
#define get_DE() ((c.D<<8) | c.E)
#define get_HL() ((c.H<<8) | c.L)
/* Flags */
#define set_Z(x) c.F = ((c.F&0x7F) | ((x)<<7))
#define set_N(x) c.F = ((c.F&0xBF) | ((x)<<6))
#define set_H(x) c.F = ((c.F&0xDF) | ((x)<<5))
#define set_C(x) c.F = ((c.F&0xEF) | ((x)<<4))
#define flag_Z !!((c.F & 0x80))
#define flag_N !!((c.F & 0x40))
#define flag_H !!((c.F & 0x20))
#define flag_C !!((c.F & 0x10))
/* Opcodes */
#define INC(x) \
x++; \
set_Z(!x); \
set_H((x & 0xF) == 0); \
set_N(0); \
c.cycles += 1;
#define DEC(x) \
x--; \
set_Z(!x); \
set_N(1); \
set_H((x & 0xF) == 0xF); \
c.cycles += 1;
#define LDRR(x, y) \
x = y; \
c.cycles += 1;
#define LDRIMM8(x) \
x = mem_get_byte(c.PC); \
c.PC += 1; \
c.cycles += 2;
#define ANDR(x) \
c.A &= x; \
set_Z(!c.A); \
set_H(1); \
set_N(0); \
set_C(0); \
c.cycles += 1;
#define XORR(x) \
c.A ^= x; \
set_Z(!c.A); \
set_H(0); \
set_N(0); \
set_C(0); \
c.cycles += 1;
#define ORR(x) \
c.A |= x; \
set_Z(!c.A); \
set_H(0); \
set_N(0); \
set_C(0); \
c.cycles += 1;
#define CPR(x) \
set_C((c.A - x) < 0); \
set_H(((c.A - x)&0xF) > (c.A&0xF)); \
set_Z(c.A == x); \
set_N(1); \
c.cycles += 1;
#define SUBR(x) \
set_C((c.A - x) < 0); \
set_H(((c.A - x)&0xF) > (c.A&0xF)); \
c.A -= x; \
set_Z(!c.A); \
set_N(1); \
c.cycles += 1;
struct CPU {
unsigned char H;
unsigned char L;
unsigned char D;
unsigned char E;
unsigned char B;
unsigned char C;
unsigned char A;
unsigned char F;
unsigned short SP;
unsigned short PC;
unsigned int cycles;
};
static struct CPU c;
static int is_debugged;
static int halted;
static int ei_flag;
void cpu_init(void)
{
set_AF(0x01B0);
set_BC(0x0013);
set_DE(0x00D8);
set_HL(0x014D);
c.SP = 0xFFFE;
#ifdef DEBUG
c.PC = 0x0100;
#else
c.PC = 0;
#endif
c.cycles = 0;
is_debugged = 0;
}
static unsigned short get_word_ticked(unsigned short i)
{
unsigned short word;
word = mem_get_byte(i);
c.cycles += 1;
timer_cycle();
word |= (mem_get_byte(i+1)<<8);
c.cycles += 1;
timer_cycle();
return word;
}
static void write_word_ticked(unsigned short d, unsigned short i)
{
mem_write_byte(d+1, i >> 8);
c.cycles += 1;
timer_cycle();
mem_write_byte(d, i & 0xFF);
c.cycles += 1;
timer_cycle();
}
static void RLC(unsigned char reg)
{
unsigned char t, old;
switch(reg)
{
case 0: /* B */
old = !!(c.B&0x80);
c.B = (c.B << 1) | old;
set_C(old);
set_Z(!c.B);
break;
case 1: /* C */
old = !!(c.C&0x80);
set_C(old);
c.C = c.C<<1 | old;
set_Z(!c.C);
break;
case 2: /* D */
old = !!(c.D&0x80);
set_C(old);
c.D = c.D<<1 | old;
set_Z(!c.D);
break;
case 3: /* E */
old = !!(c.E&0x80);
set_C(old);
c.E = c.E<<1 | old;
set_Z(!c.E);
break;
case 4: /* H */
old = !!(c.H&0x80);
set_C(old);
c.H = c.H<<1 | old;
set_Z(!c.H);
break;
case 5: /* L */
old = !!(c.L&0x80);
set_C(old);
c.L = c.L<<1 | old;
set_Z(!c.L);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
old = !!(t&0x80);
set_C(old);
t = t<<1 | old;
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
set_Z(!t);
break;
case 7: /* A */
old = !!(c.A&0x80);
c.A = (c.A<<1) | old;
set_C(old);
set_Z(!c.A);
break;
}
set_N(0);
set_H(0);
}
static void RRC(unsigned char reg)
{
unsigned char t, old;
switch(reg)
{
case 0: /* B */
old = c.B&1;
set_C(old);
c.B = c.B>>1 | old<<7;
set_Z(!c.B);
break;
case 1: /* C */
old = c.C&1;
set_C(old);
c.C = c.C>>1 | old<<7;
set_Z(!c.C);
break;
case 2: /* D */
old = c.D&1;
set_C(old);
c.D = c.D>>1 | old<<7;
set_Z(!c.D);
break;
case 3: /* E */
old = c.E&1;
set_C(old);
c.E = c.E>>1 | old<<7;
set_Z(!c.E);
break;
case 4: /* H */
old = c.H&1;
set_C(old);
c.H = c.H>>1 | old<<7;
set_Z(!c.H);
break;
case 5: /* L */
old = c.L&1;
set_C(old);
c.L = c.L>>1 | old<<7;
set_Z(!c.L);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
old = t;
set_C(old);
t = t>>1 | old<<7;
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
set_Z(!t);
break;
case 7: /* A */
old = c.A&1;
set_C(old);
c.A = c.A>>1 | old<<7;
set_Z(!c.A);
break;
}
set_N(0);
set_H(0);
}
static void RL(unsigned char reg)
{
unsigned char t, t2;
switch(reg)
{
case 0: /* B */
t2 = flag_C;
set_C(!!(c.B&0x80));
c.B = (c.B << 1) | !!(t2);
set_Z(!c.B);
break;
case 1: /* C */
t2 = flag_C;
set_C(!!(c.C&0x80));
c.C = (c.C << 1) | !!(t2);
set_Z(!c.C);
break;
case 2: /* D */
t2 = flag_C;
set_C(!!(c.D&0x80));
c.D = (c.D << 1) | !!(t2);
set_Z(!c.D);
break;
case 3: /* E */
t2 = flag_C;
set_C(!!(c.E&0x80));
c.E = (c.E << 1) | !!(t2);
set_Z(!c.E);
break;
case 4: /* H */
t2 = flag_C;
set_C(!!(c.H&0x80));
c.H = (c.H << 1) | !!(t2);
set_Z(!c.H);
break;
case 5: /* L */
t2 = flag_C;
set_C(!!(c.L&0x80));
c.L = (c.L << 1) | !!(t2);
set_Z(!c.L);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
t2 = flag_C;
set_C(!!(t&0x80));
t = (t << 1) | !!(t2);
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
set_Z(!t);
break;
case 7: /* A */
t2 = flag_C;
set_C(!!(c.A&0x80));
c.A = (c.A << 1) | !!(t2);
set_Z(!c.A);
break;
}
set_N(0);
set_H(0);
}
static void RR(unsigned char reg)
{
unsigned char t, t2;
switch(reg)
{
case 0: /* B */
t2 = flag_C;
set_C(c.B&1);
c.B = (c.B >> 1) | t2<<7;
set_Z(!c.B);
break;
case 1: /* C */
t2 = flag_C;
set_C(c.C&1);
c.C = (c.C >> 1) | t2<<7;
set_Z(!c.C);
break;
case 2: /* D */
t2 = flag_C;
set_C(c.D&1);
c.D = (c.D >> 1) | t2<<7;
set_Z(!c.D);
break;
case 3: /* E */
t2 = flag_C;
set_C(c.E&1);
c.E = (c.E >> 1) | t2<<7;
set_Z(!c.E);
break;
case 4: /* H */
t2 = flag_C;
set_C(c.H&1);
c.H = (c.H >> 1) | t2<<7;
set_Z(!c.H);
break;
case 5: /* L */
t2 = flag_C;
set_C(c.L&1);
c.L = (c.L >> 1) | t2<<7;
set_Z(!c.L);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
t2 = flag_C;
set_C(t&1);
t = (t >> 1) | t2<<7;
set_Z(!t);
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
break;
case 7: /* A */
t2 = flag_C;
set_C(c.A&1);
c.A = (c.A >> 1) | (t2<<7);
set_Z(!c.A);
break;
}
set_N(0);
set_H(0);
}
static void SLA(unsigned char reg)
{
unsigned char t;
switch(reg)
{
case 0: /* B */
set_C(!!(c.B & 0x80));
c.B = c.B << 1;
set_Z(!c.B);
break;
case 1: /* C */
set_C(!!(c.C & 0x80));
c.C = c.C << 1;
set_Z(!c.C);
break;
case 2: /* D */
set_C(!!(c.D & 0x80));
c.D = c.D << 1;
set_Z(!c.D);
break;
case 3: /* E */
set_C(!!(c.E & 0x80));
c.E = c.E << 1;
set_Z(!c.E);
break;
case 4: /* H */
set_C(!!(c.H & 0x80));
c.H = c.H << 1;
set_Z(!c.H);
break;
case 5: /* L */
set_C(!!(c.L & 0x80));
c.L = c.L << 1;
set_Z(!c.L);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
set_C(!!(t & 0x80));
t = t << 1;
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
set_Z(!t);
break;
case 7: /* A */
set_C(!!(c.A & 0x80));
c.A = c.A << 1;
set_Z(!c.A);
break;
}
set_H(0);
set_N(0);
}
static void SRA(unsigned char reg)
{
unsigned char old, t;
switch(reg)
{
case 0: /* B */
set_C(c.B&1);
old = c.B&0x80;
c.B = c.B >> 1 | old;
set_Z(!c.B);
break;
case 1: /* C */
set_C(c.C&1);
old = c.C&0x80;
c.C = c.C >> 1 | old;
set_Z(!c.C);
break;
case 2: /* D */
set_C(c.D&1);
old = c.D&0x80;
c.D = c.D >> 1 | old;
set_Z(!c.D);
break;
case 3: /* E */
set_C(c.E&1);
old = c.E&0x80;
c.E = c.E >> 1 | old;
set_Z(!c.E);
break;
case 4: /* H */
set_C(c.H&1);
old = c.H&0x80;
c.H = c.H >> 1 | old;
set_Z(!c.H);
break;
case 5: /* L */
set_C(c.L&1);
old = c.L&0x80;
c.L = c.L >> 1 | old;
set_Z(!c.L);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
set_C(t&1);
old = t&0x80;
t = t >> 1 | old;
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
set_Z(!t);
break;
case 7: /* A */
set_C(c.A&1);
old = c.A&0x80;
c.A = c.A >> 1 | old;
set_Z(!c.A);
break;
}
set_H(0);
set_N(0);
}
static void SRL(unsigned char reg)
{
unsigned char t;
switch(reg)
{
case 0: /* B */
set_C(c.B & 1);
c.B = c.B >> 1;
set_Z(!c.B);
break;
case 1: /* C */
set_C(c.C & 1);
c.C = c.C >> 1;
set_Z(!c.C);
break;
case 2: /* D */
set_C(c.D & 1);
c.D = c.D >> 1;
set_Z(!c.D);
break;
case 3: /* E */
set_C(c.E & 1);
c.E = c.E >> 1;
set_Z(!c.E);
break;
case 4: /* H */
set_C(c.H & 1);
c.H = c.H >> 1;
set_Z(!c.H);
break;
case 5: /* L */
set_C(c.L & 1);
c.L = c.L >> 1;
set_Z(!c.L);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
set_C(t & 1);
t = t >> 1;
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
set_Z(!t);
break;
case 7: /* A */
set_C(c.A & 1);
c.A = c.A >> 1;
set_Z(!c.A);
break;
}
set_H(0);
set_N(0);
}
static void SWAP(unsigned char reg)
{
unsigned char t;
switch(reg)
{
case 0: /* B */
c.B = ((c.B&0xF)<<4) | ((c.B&0xF0)>>4);
c.F = (!c.B)<<7;
break;
case 1: /* C */
c.C = ((c.C&0xF)<<4) | ((c.C&0xF0)>>4);
c.F = (!c.C)<<7;
break;
case 2: /* D */
c.D = ((c.D&0xF)<<4) | ((c.D&0xF0)>>4);
c.F = (!c.D)<<7;
break;
case 3: /* E */
c.E = ((c.E&0xF)<<4) | ((c.E&0xF0)>>4);
c.F = (!c.E)<<7;
break;
case 4: /* H */
c.H = ((c.H&0xF)<<4) | ((c.H&0xF0)>>4);
c.F = (!c.H)<<7;
break;
case 5: /* L */
c.L = ((c.L&0xF)<<4) | ((c.L&0xF0)>>4);
c.F = (!c.L)<<7;
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
t = ((t&0xF)<<4) | ((t&0xF0)>>4);
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
c.F = (!t)<<7;
break;
case 7: /* A */
c.A = ((c.A&0xF)<<4) | ((c.A&0xF0)>>4);
c.F = (!c.A)<<7;
break;
}
}
static void BIT(unsigned char bit, unsigned char reg)
{
unsigned char t, f = 0 /* Make GCC happy */;
switch(reg)
{
case 0: /* B */
f = !(c.B & bit);
break;
case 1: /* C */
f = !(c.C & bit);
break;
case 2: /* D */
f = !(c.D & bit);
break;
case 3: /* E */
f = !(c.E & bit);
break;
case 4: /* H */
f = !(c.H & bit);
break;
case 5: /* L */
f = !(c.L & bit);
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
f = !(t & bit);
break;
case 7: /* A */
f = !(c.A & bit);
break;
}
set_Z(f);
set_N(0);
set_H(1);
}
static void RES(unsigned char bit, unsigned char reg)
{
unsigned char t;
switch(reg)
{
case 0: /* B */
c.B &= ~bit;
break;
case 1: /* C */
c.C &= ~bit;
break;
case 2: /* D */
c.D &= ~bit;
break;
case 3: /* E */
c.E &= ~bit;
break;
case 4: /* H */
c.H &= ~bit;
break;
case 5: /* L */
c.L &= ~bit;
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
t &= ~bit;
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
break;
case 7: /* A */
c.A &= ~bit;
break;
}
}
static void SET(unsigned char bit, unsigned char reg)
{
unsigned char t;
switch(reg)
{
case 0: /* B */
c.B |= bit;
break;
case 1: /* C */
c.C |= bit;
break;
case 2: /* D */
c.D |= bit;
break;
case 3: /* E */
c.E |= bit;
break;
case 4: /* H */
c.H |= bit;
break;
case 5: /* L */
c.L |= bit;
break;
case 6: /* (HL) */
c.cycles += 1;
timer_cycle();
t = mem_get_byte(get_HL());
t |= bit;
c.cycles += 1;
timer_cycle();
mem_write_byte(get_HL(), t);
break;
case 7: /* A */
c.A |= bit;
break;
}
}
/*
00000xxx = RLC xxx
00001xxx = RRC xxx
00010xxx = RL xxx
00011xxx = RR xxx
00100xxx = SLA xxx
00101xxx = SRA xxx
00110xxx = SWAP xxx
00111xxx = SRL xxx
01yyyxxx = BIT yyy, xxx
10yyyxxx = RES yyy, xxx
11yyyxxx = SET yyy, xxx
*/
static void decode_CB(unsigned char t)
{
unsigned char reg, opcode, bit;
void (*f[])(unsigned char) = {RLC, RRC, RL, RR, SLA, SRA, SWAP, SRL};
void (*f2[])(unsigned char, unsigned char) = {BIT, RES, SET};
c.cycles += 1;
reg = t&7;
opcode = t>>3;
if(opcode < 8)
{
f[opcode](reg);
c.cycles += 1;
return;
}
bit = opcode&7;
opcode >>= 3;
f2[opcode-1](1<<bit, reg);
c.cycles += 1;
}
int cpu_halted(void)
{
return halted;
}
unsigned int cpu_get_cycles(void)
{
return c.cycles;
}
static int halt_bug = 0;
void cpu_unhalt(void)
{
halted = 0;
}
void cpu_halt(void)
{
halted = 1;
}
unsigned int cpu_getpc(void)
{
return c.PC;
}
void cpu_interrupt_begin(void)
{
halted = 0;
c.SP -= 2;
mem_write_word(c.SP, c.PC);
c.cycles += 2;
}
void cpu_interrupt(unsigned short n)
{
c.PC = n;
c.cycles += 2;
interrupt_disable();
c.cycles += 1;
}
void cpu_print_debug(void)
{
printf("PC: %04X AF: %02X%02X, BC: %02X%02X, DE: %02X%02X, HL: %02X%02X, SP: %04X, cycles: %d\n",
c.PC, c.A, c.F, c.B, c.C, c.D, c.E, c.H, c.L, c.SP, c.cycles);
}
int cpu_cycle(void)
{
unsigned char b, t;
unsigned short s;
unsigned int i;
/* If any interrupts are pending, do them now */
if(!ei_flag)
interrupt_flush();
else
{
ei_flag = 0;
interrupt_enable();
}
/* If the cpu is halted, do nothing instead */
if(halted)
{
c.cycles += 1;
return 1;
}
#ifdef DEBUG
if(c.PC == 0x100)
is_debugged = 1;
if(c.PC == 0xC0BD && is_debugged)
{is_debugged = 0; exit(0);}
#endif
if(is_debugged)
cpu_print_debug();
/* Otherwise, execute as normal */
b = mem_get_byte(c.PC);
if(halt_bug)
halt_bug = 0;
else
c.PC++;
switch(b)
{
case 0x00: /* NOP */
c.cycles += 1;
break;
case 0x01: /* LD BC, imm16 */
s = mem_get_word(c.PC);
set_BC(s);
c.PC += 2;
c.cycles += 3;
break;
case 0x02: /* LD (BC), A */
c.cycles += 1;
timer_cycle();
mem_write_byte(get_BC(), c.A);
c.cycles += 1;
break;
case 0x03: /* INC BC */
set_BC(get_BC()+1);
c.cycles += 2;
break;
case 0x04: /* INC B */
INC(c.B);
break;
case 0x05: /* DEC B */
DEC(c.B);
break;
case 0x06: /* LD B, imm8 */
LDRIMM8(c.B);
break;
case 0x07: /* RLCA */
RLC(7);
set_Z(0);
c.cycles += 1;
break;
case 0x08: /* LD (imm16), SP */
c.cycles += 3;
timer_cycle();
mem_write_word(mem_get_word(c.PC), c.SP);
c.PC += 2;
c.cycles += 2;
break;
case 0x09: /* ADD HL, BC */
i = get_HL() + get_BC();
set_N(0);
set_C(i >= 0x10000);
set_H((i&0xFFF) < (get_HL()&0xFFF));
set_HL(i&0xFFFF);
c.cycles += 2;
break;
case 0x0A: /* LD A, (BC) */
c.cycles += 1;
timer_cycle();
c.A = mem_get_byte(get_BC());
c.cycles += 1;
break;
case 0x0B: /* DEC BC */
s = get_BC();
s--;
set_BC(s);
c.cycles += 2;
break;
case 0x0C: /* INC C */
INC(c.C);
break;
case 0x0D: /* DEC C */
DEC(c.C);
break;
case 0x0E: /* LD C, imm8 */
LDRIMM8(c.C);
break;
case 0x0F: /* RRCA */
RRC(7);
set_Z(0);
c.cycles += 1;
break;
case 0x11: /* LD DE, imm16 */
s = mem_get_word(c.PC);
set_DE(s);
c.PC += 2;
c.cycles += 3;
break;
case 0x12: /* LD (DE), A */
c.cycles += 1;
timer_cycle();
mem_write_byte(get_DE(), c.A);
c.cycles += 1;
break;
case 0x13: /* INC DE */
s = get_DE();
s++;
set_DE(s);
c.cycles += 2;
break;
case 0x14: /* INC D */
INC(c.D);
break;
case 0x15: /* DEC D */
DEC(c.D);
break;
case 0x16: /* LD D, imm8 */
LDRIMM8(c.D);
break;
case 0x17: /* RLA */
RL(7);
set_Z(0);
c.cycles += 1;
break;
case 0x18: /* JR rel8 */
c.PC += (signed char)mem_get_byte(c.PC) + 1;
c.cycles += 3;