From fe2fca3b8ec29ed01eb8350e6358c06da3a705fc Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Tue, 30 Jan 2024 23:31:38 +0000 Subject: [PATCH] Backport [RISCV] Graduate Zicond to non-experimental (#79811) (#80018) The Zicond extension was ratified in the last few months, with no changes that affect the LLVM implementation. Although there's surely more tuning that could be done about when to select Zicond or not, there are no known correctness issues. Therefore, we should mark support as non-experimental. (cherry-picked from commit d833b9d677c9dd0a35a211e2fdfada21ea9a464b) --- .../CodeGen/RISCV/riscv-func-attr-target.c | 2 +- .../test/Preprocessor/riscv-target-features.c | 16 +++--- llvm/docs/RISCVUsage.rst | 4 +- llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Support/RISCVISAInfo.cpp | 3 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td | 2 - llvm/test/CodeGen/RISCV/attributes.ll | 4 +- llvm/test/CodeGen/RISCV/cmov-branch-opt.ll | 4 +- llvm/test/CodeGen/RISCV/condbinops.ll | 4 +- llvm/test/CodeGen/RISCV/condops.ll | 4 +- .../CodeGen/RISCV/select-binop-identity.ll | 4 +- llvm/test/CodeGen/RISCV/select.ll | 4 +- .../CodeGen/RISCV/short-forward-branch-opt.ll | 2 +- llvm/test/CodeGen/RISCV/xaluo.ll | 4 +- llvm/test/MC/RISCV/rv32zicond-invalid.s | 4 +- llvm/test/MC/RISCV/rv32zicond-valid.s | 12 ++--- llvm/unittests/Support/RISCVISAInfoTest.cpp | 52 +++++++++---------- 18 files changed, 60 insertions(+), 68 deletions(-) diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c index 7d3362e84e7588..f216eaf735b4a8 100644 --- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c +++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c @@ -39,7 +39,7 @@ __attribute__((target("cpu=sifive-u54"))) void testAttrCpuOnly() {} // CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" } // CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" } // CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" } -// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+experimental-zicond,+f,+m,+save-restore,+v,+zbb,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } +// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } // Make sure we append negative features if we override the arch // CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } // CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 39d2c66f14b23f..30697af89c2ebe 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -764,6 +764,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICNTR-EXT %s // CHECK-ZICNTR-EXT: __riscv_zicntr 2000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s +// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izicsr2p0 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICSR-EXT %s @@ -1332,14 +1340,6 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s // CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}} -// RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s -// RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s -// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}} - // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zimop0p1 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 6fdc945ad27078..ba292ea39c8a8a 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -130,6 +130,7 @@ on support follow. ``Zicclsm`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Ziccrse`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Zicntr`` (`See Note <#riscv-i2p1-note>`__) + ``Zicond`` Supported ``Zicsr`` (`See Note <#riscv-i2p1-note>`__) ``Zifencei`` (`See Note <#riscv-i2p1-note>`__) ``Zihintntl`` Supported @@ -234,9 +235,6 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `0.4 draft specification `__. -``experimental-zicond`` - LLVM implements the `1.0-rc1 draft specification `__. - ``experimental-ztso`` LLVM implements the `v0.1 proposed specification `__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 7b6a3f10d63777..0e70a4e08159e9 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -181,6 +181,7 @@ Changes to the RISC-V Backend specification. * The Smepmp 1.0 extension is now supported. * ``-mcpu=sifive-p670`` was added. +* Support for the Zicond extension is no longer experimental. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 3c02492e99f1db..db2e4ca92ae40a 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -128,6 +128,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zicclsm", {1, 0}}, {"ziccrse", {1, 0}}, {"zicntr", {2, 0}}, + {"zicond", {1, 0}}, {"zicsr", {2, 0}}, {"zifencei", {2, 0}}, {"zihintntl", {1, 0}}, @@ -200,8 +201,6 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zicfilp", {0, 4}}, {"zicfiss", {0, 4}}, - {"zicond", {1, 0}}, - {"zimop", {0, 1}}, {"ztso", {0, 1}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e913ac6aa2629e..26451c80f57b42 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -72,7 +72,7 @@ def FeatureStdExtZicntr [FeatureStdExtZicsr]>; def FeatureStdExtZicond - : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true", + : SubtargetFeature<"zicond", "HasStdExtZicond", "true", "'Zicond' (Integer Conditional Operations)">; def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">, AssemblerPredicate<(all_of FeatureStdExtZicond), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td index 0790a941823b1a..35d3fdae0bd79b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td @@ -8,8 +8,6 @@ // // This file describes the RISC-V instructions from the standard Integer // Conditional operations extension (Zicond). -// This version is still experimental as the 'Zicond' extension hasn't been -// ratified yet. It is based on v1.0-rc1 of the specification. // //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index b90bef7525379d..ecd14eaffcb5d5 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -84,7 +84,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s +; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s @@ -186,7 +186,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s +; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s diff --git a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll index 6ad529ea477c1a..b26bd7b889807a 100644 --- a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll @@ -3,13 +3,13 @@ ; RUN: | FileCheck -check-prefix=NOCMOV %s ; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CMOV,CMOV-NOZICOND %s -; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+experimental-zicond -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+conditional-cmv-fusion,+c,+zicond -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=CMOV,CMOV-ZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+c -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND %s -; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+experimental-zicond -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-opt,+zicond -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-ZICOND %s ; The conditional move optimization in sifive-p450 requires that only a diff --git a/llvm/test/CodeGen/RISCV/condbinops.ll b/llvm/test/CodeGen/RISCV/condbinops.ll index 87ebefcb65c7de..1a661fddacfa05 100644 --- a/llvm/test/CodeGen/RISCV/condbinops.ll +++ b/llvm/test/CodeGen/RISCV/condbinops.ll @@ -3,8 +3,8 @@ ; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS ; RUN: llc -mtriple=riscv64 -mattr=+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND +; RUN: llc -mtriple=riscv32 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND +; RUN: llc -mtriple=riscv64 -mattr=+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND define i32 @shl32(i32 %x, i32 %y, i1 %c) { ; RV32I-LABEL: shl32: diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index 23f219c2487ebc..8e53782b5dcd78 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -3,8 +3,8 @@ ; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs < %s | FileCheck %s -check-prefix=RV64I ; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xventanacondops < %s | FileCheck %s -check-prefix=RV64XVENTANACONDOPS ; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+xtheadcondmov < %s | FileCheck %s -check-prefix=RV64XTHEADCONDMOV -; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV32ZICOND -; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+experimental-zicond < %s | FileCheck %s -check-prefix=RV64ZICOND +; RUN: llc -mtriple=riscv32 -target-abi=ilp32f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV32ZICOND +; RUN: llc -mtriple=riscv64 -target-abi=lp64f -mattr=+f,+zbs,+zicond < %s | FileCheck %s -check-prefix=RV64ZICOND define i64 @zero1(i64 %rs1, i1 zeroext %rc) { ; RV32I-LABEL: zero1: diff --git a/llvm/test/CodeGen/RISCV/select-binop-identity.ll b/llvm/test/CodeGen/RISCV/select-binop-identity.ll index f45d67164d640d..83bb7f19fa2b05 100644 --- a/llvm/test/CodeGen/RISCV/select-binop-identity.ll +++ b/llvm/test/CodeGen/RISCV/select-binop-identity.ll @@ -7,9 +7,9 @@ ; RUN: | FileCheck -check-prefix=SFB64 %s ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=VTCONDOPS64 %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zicond -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32,ZICOND,ZICOND32 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zicond -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=ZICOND,ZICOND64 %s ; InstCombine canonicalizes (c ? x | y : x) to (x | (c ? y : 0)) similar for diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll index 7fa27a307757d0..7dd223df5e557e 100644 --- a/llvm/test/CodeGen/RISCV/select.ll +++ b/llvm/test/CodeGen/RISCV/select.ll @@ -2,8 +2,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32IM %s ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IM %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s +; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s +; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s define i16 @select_xor_1(i16 %A, i8 %cond) { ; RV32IM-LABEL: select_xor_1: diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll index d2ddbe99000ed0..87406f22d169d1 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck -check-prefix=NOSFB %s ; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV64SFB %s -; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond,+zbb \ +; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zicond,+zbb \ ; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=SFB,ZICOND %s ; RUN: llc -mtriple=riscv32 -mcpu=sifive-e76 -mattr=+zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV32SFB %s diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll index f878d17d5f1da6..ac67c0769f7056 100644 --- a/llvm/test/CodeGen/RISCV/xaluo.ll +++ b/llvm/test/CodeGen/RISCV/xaluo.ll @@ -3,8 +3,8 @@ ; RUN: llc < %s -mtriple=riscv64 -mattr=+m -verify-machineinstrs | FileCheck %s --check-prefix=RV64 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZBA ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zba -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZBA -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZICOND -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZICOND +; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV32ZICOND +; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs | FileCheck %s --check-prefix=RV64ZICOND ; ; Get the actual value of the overflow bit. diff --git a/llvm/test/MC/RISCV/rv32zicond-invalid.s b/llvm/test/MC/RISCV/rv32zicond-invalid.s index a350593993b525..02f5d1777b0ebc 100644 --- a/llvm/test/MC/RISCV/rv32zicond-invalid.s +++ b/llvm/test/MC/RISCV/rv32zicond-invalid.s @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 -mattr=+zicond < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=+zicond < %s 2>&1 | FileCheck %s # Use of operand modifier on register name czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zicond-valid.s b/llvm/test/MC/RISCV/rv32zicond-valid.s index e6deb81301eca7..c862f04b806788 100644 --- a/llvm/test/MC/RISCV/rv32zicond-valid.s +++ b/llvm/test/MC/RISCV/rv32zicond-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicond -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicond -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicond < %s \ +# RUN: | llvm-objdump --mattr=+zicond -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicond < %s \ +# RUN: | llvm-objdump --mattr=+zicond -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 9b7112fa2bfeb5..24ed3e2e4b0561 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -366,55 +366,51 @@ TEST(ParseArchString, RejectsDuplicateExtensionNames) { TEST(ParseArchString, RejectsExperimentalExtensionsIfNotEnableExperimentalExtension) { EXPECT_EQ( - toString( - RISCVISAInfo::parseArchString("rv64izicond", false).takeError()), + toString(RISCVISAInfo::parseArchString("rv64iztso", false).takeError()), "requires '-menable-experimental-extensions' for experimental extension " - "'zicond'"); + "'ztso'"); } TEST(ParseArchString, AcceptsExperimentalExtensionsIfEnableExperimentalExtension) { - // Note: If zicond becomes none-experimental, this test will need + // Note: If ztso becomes none-experimental, this test will need // updating (and unfortunately, it will still pass). The failure of // RejectsExperimentalExtensionsIfNotEnableExperimentalExtension will // hopefully serve as a reminder to update. - auto MaybeISAInfo = - RISCVISAInfo::parseArchString("rv64izicond", true, false); + auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv64iztso", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); - EXPECT_EQ(Exts.count("zicond"), 1U); - auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izicond1p0", true); + EXPECT_EQ(Exts.count("ztso"), 1U); + auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64iztso0p1", true); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts2 = (*MaybeISAInfo2)->getExtensions(); EXPECT_EQ(Exts2.size(), 2UL); - EXPECT_EQ(Exts2.count("zicond"), 1U); + EXPECT_EQ(Exts2.count("ztso"), 1U); } TEST(ParseArchString, RequiresExplicitVersionNumberForExperimentalExtensionByDefault) { EXPECT_EQ( - toString( - RISCVISAInfo::parseArchString("rv64izicond", true).takeError()), - "experimental extension requires explicit version number `zicond`"); + toString(RISCVISAInfo::parseArchString("rv64iztso", true).takeError()), + "experimental extension requires explicit version number `ztso`"); } TEST(ParseArchString, AcceptsUnrecognizedVersionIfNotExperimentalExtensionVersionCheck) { auto MaybeISAInfo = - RISCVISAInfo::parseArchString("rv64izicond9p9", true, false); + RISCVISAInfo::parseArchString("rv64iztso9p9", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); - EXPECT_TRUE(Exts.at("zicond") == (RISCVISAInfo::ExtensionVersion{9, 9})); + EXPECT_TRUE(Exts.at("ztso") == (RISCVISAInfo::ExtensionVersion{9, 9})); } TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) { EXPECT_EQ( - toString( - RISCVISAInfo::parseArchString("rv64izicond9p9", true).takeError()), - "unsupported version number 9.9 for experimental extension 'zicond' " - "(this compiler supports 1.0)"); + toString(RISCVISAInfo::parseArchString("rv64iztso9p9", true).takeError()), + "unsupported version number 9.9 for experimental extension 'ztso' " + "(this compiler supports 0.1)"); } TEST(ParseArchString, RejectsExtensionVersionForG) { @@ -489,16 +485,16 @@ TEST(ParseArchString, RejectsConflictingExtensions) { TEST(ToFeatures, IIsDroppedAndExperimentalExtensionsArePrefixed) { auto MaybeISAInfo1 = - RISCVISAInfo::parseArchString("rv64im_zicond", true, false); + RISCVISAInfo::parseArchString("rv64im_ztso", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded()); EXPECT_THAT((*MaybeISAInfo1)->toFeatures(), - ElementsAre("+m", "+experimental-zicond")); + ElementsAre("+m", "+experimental-ztso")); - auto MaybeISAInfo2 = RISCVISAInfo::parseArchString( - "rv32e_zicond_xventanacondops", true, false); + auto MaybeISAInfo2 = + RISCVISAInfo::parseArchString("rv32e_ztso_xventanacondops", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); EXPECT_THAT((*MaybeISAInfo2)->toFeatures(), - ElementsAre("+e", "+experimental-zicond", "+xventanacondops")); + ElementsAre("+e", "+experimental-ztso", "+xventanacondops")); } TEST(ToFeatures, UnsupportedExtensionsAreDropped) { @@ -649,10 +645,10 @@ TEST(isSupportedExtensionWithVersion, AcceptsSingleExtensionWithVersion) { TEST(getTargetFeatureForExtension, RetrieveTargetFeatureFromOneExt) { EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbb"), "zbb"); - EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zicond1p0"), - "experimental-zicond"); - EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zicond"), - "experimental-zicond"); + EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("ztso0p1"), + "experimental-ztso"); + EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("ztso"), + "experimental-ztso"); EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zihintntl1234p4321"), ""); EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zfoo"), ""); @@ -684,6 +680,7 @@ R"(All available -march extensions for RISC-V zicclsm 1.0 ziccrse 1.0 zicntr 2.0 + zicond 1.0 zicsr 2.0 zifencei 2.0 zihintntl 1.0 @@ -793,7 +790,6 @@ R"(All available -march extensions for RISC-V Experimental extensions zicfilp 0.4 This is a long dummy description zicfiss 0.4 - zicond 1.0 zimop 0.1 zacas 1.0 zfbfmin 1.0