td4.qsf

set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY td4
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name VERILOG_FILE counter.v
set_global_assignment -name VERILOG_FILE decoder.v
set_global_assignment -name VERILOG_FILE multiplexer.v
set_global_assignment -name VERILOG_FILE register.v
set_global_assignment -name VERILOG_FILE blink.v
set_global_assignment -name VERILOG_FILE td4.v
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_location_assignment PIN_56 -to OUT[0]
set_location_assignment PIN_55 -to OUT[1]
set_location_assignment PIN_54 -to OUT[2]
set_location_assignment PIN_53 -to OUT[3]
set_location_assignment PIN_28 -to CLK
set_location_assignment PIN_240 -to RSTB
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH sim_top_led -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME test_td4 -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id test_td4 
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME test_td4 -section_id test_td4
set_global_assignment -name EDA_TEST_BENCH_FILE td4test.v -section_id test_td4
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id To