__   _ __      __ __                  ___
     / /  (_) /____ / // /_ _____  ___ ____/ _ )__ _____
    / /__/ / __/ -_) _  / // / _ \/ -_) __/ _  / // (_-<
   /____/_/\__/\__/_//_/\_, / .__/\__/_/ /____/\_,_/___/
                       /___/_/

      Copyright (c) 2020-2022, LiteHyperBus Developers

[> Intro

LiteHyperBus provides a small footprint and configurable HyperBus core.

LiteHyperBus is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

Using Migen to describe the HDL allows the core to be highly and easily configurable.

LiteHyperBus can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.

[> Features

TODO

[> Getting started

TODO

[> Tests

Unit tests are available in ./test/. To run all the unit tests: ./setup.py test Tests can also be run individually: python3 -m unittest test.test_name

[> License

LiteHyperBus is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteHyperBus for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:

• tell us that you are using LiteHyperBus
• cite LiteHyperBus in publications related to research it has helped
• send us feedback and suggestions for improvements
• send us bug reports when something goes wrong
• send us the modifications and improvements you have done to LiteHyperBus.