This repository is a collection of basic arithmetic-related hardware modules defined in VHDL. Originally, these components were implemented in the Xilinx ISE Design Suite and mapped onto Xilinx Spartan FPGAs for demonstration purposes but it is possible to compile and simulate them with the open-source GHDL compiler and simulator.
The simulated behaviour can be easily displayed with the likewise open-source GTKWave viewer.
- Simple ALU with basic operations (add, and, or, left shift)
- Redundant Binary Adder
- Bitonic Sorter Network
(The detailed description of each module is placed into its own directory.)
- Add GHDL-based build and test scripts to the modules.
This library is distributed under the terms and conditions of the MPL v2.0. Copyright © 2019, 0l-l0