ADC Prj: Remove impossible clock #33

	name: Lint HDL
	on:
	push:
	pull_request:

	permissions:
	contents: read

	# Avoid multiple tests running on the same reference
	concurrency:
	group: ${{ github.workflow }}-${{ github.ref }}
	cancel-in-progress: true

	jobs:
	verible-lint:
	runs-on: ubuntu-latest
	steps:
	- uses: actions/checkout@v4
	- name: Install make
	run: \|
	sudo apt-get update
	sudo apt-get -y install make
	- uses: 3j14/verible-actions-common/install-verible@optional-github-token
	- name: Run verible-verilog-lint
	run: make verible-lint
	verilator-lint:
	runs-on: ubuntu-24.04
	steps:
	- uses: actions/checkout@v4
	- name: Clone yosys repo for simulation sources
	uses: actions/checkout@v4
	with:
	repository: YosysHQ/yosys
	path: ./yosys
	ref: main
	sparse-checkout: techlibs/xilinx/cells_sim.v

	- name: Copy cells_sim.v to /usr/share/yosys/xilinx/
	run: \|
	sudo mkdir -p /usr/share/yosys/xilinx
	sudo cp ./yosys/techlibs/xilinx/cells_sim.v /usr/share/yosys/xilinx/

	- name: Install verilator and make
	run: \|
	sudo apt-get update
	sudo apt-get -y install verilator make

	- name: Run verilator lint
	run: make verilator-lint

Provide feedback