pipeline-cpu

A pipeline cpu with nested interrupt, realized in logisim and FPGA

support instruction

add, addi, addiu, addu, and, andi, sll, sra, srl, sub, or, ori, nor, lw, sw, beq, bne, slt, sti, sltu, j, jal, jr, syscall, mfc0, mtc0, eret, srlv, lbu, bgez, sltiu

running result

** main program:**

the cycles is 2301

interrupt1:

support extend instructions: bgez, lbu, srlv, sltiu, code in 'testcase/pipeline_int.asm

interrupt2:

code in 'testcase/pipeline_int.asm

interrupt3:

code in 'testcase/pipeline_int.asm