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Merge develop into main #880

Merged
merged 640 commits into from
Feb 5, 2022

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@mbrossard mbrossard commented Oct 21, 2021

  • Support for GCC and armclang
  • Update to CMSIS-DAP 2.1
  • Upgrade to CMSIS-RTOS2 and RTX5 (for GCC and armclang)
  • Newlpc5xx HIC
  • Newnrf52820 HIC
  • CI with GitHub Actions
  • Many improvements, fixes and clean-ups

mbrossard and others added 30 commits October 21, 2021 22:32
-Enabled UART HW overrun interrupt
-Optimized time spent in I2C IRQ handler by moving bufffer clearing outside
-Add I2C busy singaling mechanism
-Add I2C ASCII encoding window command feature
- define DEVELOP_IN_NRF52833
- disable JTAG and SWO
mbrossard and others added 26 commits January 12, 2022 18:47
As this library is only used by micro:bit and not generic enough.
…me it.

Also change the magic key used to identify valid data in flash
as the structure has changed.
…ents (ARMmbed#932)

* Re-apply "LPC55xx: Improve UART TX performance."

This reverts commit 08d6cb5.

* lpc55xx_hic: Fix circ_buf asserts

The assert should be checking that there are more or the same number of
bytes in the circular buffer than those that are being removed, not the
other way around. This was causing an erroneous assert condition in the
UART interrupt handler.

* lpc55xx_hic: Abort ongoing TX when changing the UART config

Changing the UART config (baudrate, parity, etc) was clearing the RX and
TX buffers, but if there was an ongoing TX transfer it would try to
remove the bytes from the TX buffer after the transfer completes. This
patch cancels any ongoing TX transfer when clearing the buffers on
config changes and UART reset.
Also use memcpy in i2c_clearTxBuffer().
As soon as target was done I2C reading from DAPLink it was getting
ready the next messsage. Sometime it would send the next I2C write
before the TX callback had time to run in the RTOS main thread.
The state should be changed when the target request DAPLink to go into
MB_POWER_DOWN mode, not when the reset button has been long pressed.
Nordic EasyDMA needs the data to be 32-bit aligned.

The KL27 code to write to flash asserts also for alignment, so
ensure the buffers sent to storage_program_flash() are aligned too.
When a 32 bytes data (or custom data) record is processed and the
`HEX_PARSE_UNALIGNED` status is triggered, the `line.buffer` index
variable `idx` is set to a value one-too-large and causes a write
out-of-bounds, which can corrupt other data placed right after it
in RAM.

Increasing the hex_blob pointer before exiting the function ensures
the start of new record is processed before the
`line.buf[idx] |= ctoh((uint8_t)(*hex_blob)) & 0xf;`, which resets
`idx` back to zero.

More info in PR  ARMmbed#936
@mbrossard mbrossard force-pushed the feature/merge-develop-to-main branch from 8853323 to fbb36f8 Compare February 5, 2022 04:50
@mathias-arm mathias-arm marked this pull request as ready for review February 5, 2022 04:51
@mathias-arm mathias-arm requested a review from flit February 5, 2022 04:51
@mathias-arm mathias-arm merged commit c782a5b into ARMmbed:main Feb 5, 2022
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