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M487: Get around h/w limit with WDT reset from PD
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Use WKT to get around this h/w limit
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ccli8 committed Apr 22, 2021
1 parent 0be7685 commit 88b6d19
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Showing 2 changed files with 46 additions and 6 deletions.
28 changes: 25 additions & 3 deletions targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2015-2016 Nuvoton
/*
* Copyright (c) 2015-2016, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand Down Expand Up @@ -57,7 +59,7 @@ void mbed_sdk_init(void)

/* Set PCLK0/PCLK1 to HCLK/2 */
CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2); // PCLK divider set 2

#if DEVICE_ANALOGIN
/* Vref connect to internal */
SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_3_0V;
Expand All @@ -69,4 +71,24 @@ void mbed_sdk_init(void)

/* Lock protected registers */
SYS_LockReg();

/* Get around h/w limit with WDT reset from PD */
if (SYS_IS_WDT_RST()) {
/* Re-unlock protected clock setting */
SYS_UnlockReg();

/* Set up DPD power down mode */
CLK->PMUSTS |= CLK_PMUSTS_CLRWK_Msk;
CLK->PMUSTS |= CLK_PMUSTS_TMRWK_Msk;
CLK_SetPowerDownMode(CLK_PMUCTL_PDMSEL_DPD);

/* Set up PMU wakeup timer, wakeup interval must be WKTMRIS_512 51.2 ms at least */
CLK_SET_WKTMR_INTERVAL(CLK_PMUCTL_WKTMRIS_512);
CLK_ENABLE_WKTMR();

CLK_PowerDown();

/* Lock protected registers */
SYS_LockReg();
}
}
24 changes: 21 additions & 3 deletions targets/TARGET_NUVOTON/TARGET_M480/reset_reason.c
Original file line number Diff line number Diff line change
@@ -1,5 +1,7 @@
/* mbed Microcontroller Library
* Copyright (c) 2017-2018 Nuvoton
/*
* Copyright (c) 2017-2018, Nuvoton Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand Down Expand Up @@ -37,6 +39,12 @@ reset_reason_t hal_reset_reason_get(void)
reset_reason_t reset_reason_cast;
uint32_t reset_reason_count = 0;

/* Get around h/w limit with WDT reset from PD */
if (CLK->PMUSTS & CLK_PMUSTS_TMRWK_Msk) {
/* Per test, these reset reason flags will set with WKT reset. Clear them for this resolution. */
SYS_CLEAR_RST_SOURCE(SYS_RSTSTS_PINRF_Msk | SYS_RSTSTS_PORF_Msk);
}

if (SYS_IS_POR_RST()) {
reset_reason_cast = RESET_REASON_POWER_ON;
reset_reason_count ++;
Expand All @@ -47,7 +55,8 @@ reset_reason_t hal_reset_reason_get(void)
reset_reason_count ++;
}

if (SYS_IS_WDT_RST()) {
/* Get around h/w limit with WDT reset from PD */
if (SYS_IS_WDT_RST() || (CLK->PMUSTS & CLK_PMUSTS_TMRWK_Msk)) {
reset_reason_cast = RESET_REASON_WATCHDOG;
reset_reason_count ++;
}
Expand Down Expand Up @@ -101,6 +110,15 @@ uint32_t hal_reset_reason_get_raw(void)
void hal_reset_reason_clear(void)
{
SYS_CLEAR_RST_SOURCE(SYS->RSTSTS);

/* Re-unlock protected clock setting */
SYS_UnlockReg();

/* Get around h/w limit with WDT reset from PD */
CLK->PMUSTS |= (CLK_PMUSTS_CLRWK_Msk | CLK_PMUSTS_TMRWK_Msk);

/* Lock protected registers */
SYS_LockReg();
}

#endif

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