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RISC-V CPU with R,I,S,B & J instruction set implemented in Verilog HDL.

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Name		Name	Last commit message	Last commit date
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doc		doc
riscv-vivado/risc-v		riscv-vivado/risc-v
rtl		rtl
test		test
README.md		README.md

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RISC-V

RISC-V CPU with R,I,S,B & J instruction set implemented in Verilog HDL.

Supported instruction set:

R-Type: add, or, sub, and
I-Type: addi, andi, ori, lw, jalr
S-Type: sw
B-Type: beq, bne
J-Type: jal

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RISC-V CPU with R,I,S,B & J instruction set implemented in Verilog HDL.

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