Design and implementation of a Single-Cycle RISC-V processor in verilog, supporting the RV32I ISA
This Design supports all the instructions of the RV32I ISA.
Start a project in any Hardware Design suite (Vivado or Quartus Prime). Clone this repository and build using the verilog designs.
Please feel free to open a PR for contributing or for any issues. This design can further be improved to accomodate the RV32M, RV32A ISA.