Enhanced STM32F7xx MPU configuration in mcuconf.h.

git-svn-id: https://svn.code.sf.net/p/chibios/code/branches/stable_21.11.x@16217 085d63ac-f8f8-4fb4-a5e5-c089fd4f3ff4
ArduPilot · Apr 13, 2023 · ad5f683 · ad5f683
1 parent 49ff401
commit ad5f683
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Showing 22 changed files with 274 additions and 42 deletions.
diff --git a/demos/STM32/NASA-OSAL-STM32F746G-DISCOVERY/cfg/mcuconf.h b/demos/STM32/NASA-OSAL-STM32F746G-DISCOVERY/cfg/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h b/demos/STM32/NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32-LWIP-FATFS-USB-HTTPS/cfg/stm32f746_discovery/mcuconf.h b/demos/STM32/RT-STM32-LWIP-FATFS-USB-HTTPS/cfg/stm32f746_discovery/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f746_discovery/mcuconf.h b/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f746_discovery/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f769_discovery/mcuconf.h b/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f769_discovery/mcuconf.h
@@ -39,9 +39,21 @@
 #define STM32F779_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -98,7 +110,6 @@
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
 #define STM32_SDMMC2SEL                     STM32_SDMMC2SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h
@@ -38,9 +38,21 @@
 #define STM32F733_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -95,7 +107,6 @@
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
 #define STM32_SDMMC2SEL                     STM32_SDMMC2SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32F746G-DISCOVERY/cfg/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h
@@ -39,9 +39,21 @@
 #define STM32F779_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -98,7 +110,6 @@
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
 #define STM32_SDMMC2SEL                     STM32_SDMMC2SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32F769I-DISCOVERY/cfg/mcuconf.h
@@ -39,9 +39,21 @@
 #define STM32F779_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -98,7 +110,6 @@
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
 #define STM32_SDMMC2SEL                     STM32_SDMMC2SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.

diff --git a/readme.txt b/readme.txt
@@ -74,6 +74,7 @@
 *****************************************************************************
 
 *** 21.11.4 ***
+- NEW: Enhanced STM32F7xx MPU configuration in mcuconf.h.
 - NEW: I2C slave support in HAL high level driver.
 - NEW: Added settings for STM32 OCTOSPIv1 and OCTOSPIv2 TCR bits SSHIFT and
        DHQC.

diff --git a/testex/STM32/STM32F7xx/SPI-ADXL355/cfg/mcuconf.h b/testex/STM32/STM32F7xx/SPI-ADXL355/cfg/mcuconf.h
@@ -36,9 +36,21 @@
 #define STM32F756_MCUCONF
 
 /*
- * HAL driver system settings.
+ * General settings.
  */
 #define STM32_NO_INIT                       FALSE
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE                TRUE
+#define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
+#define STM32_NOCACHE_RBAR                  0x2004C000U
+#define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
+
+/*
+ * HAL driver system settings.
+ */
 #define STM32_PVD_ENABLE                    FALSE
 #define STM32_PLS                           STM32_PLS_LEV0
 #define STM32_BKPRAM_ENABLE                 FALSE
@@ -94,7 +106,6 @@
 #define STM32_CECSEL                        STM32_CECSEL_LSE
 #define STM32_CK48MSEL                      STM32_CK48MSEL_PLL
 #define STM32_SDMMC1SEL                     STM32_SDMMC1SEL_PLL48CLK
-#define STM32_SRAM2_NOCACHE                 FALSE
 
 /*
  * IRQ system settings.