daemon_cl: Fixes PPS out-of-phase issue. #333
Merged
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From I210 datasheet section
7.8.3.3.3 "Synchronized Output Clock on SDP Pins":
The clock out drives initially a logical '0' level on the selected SDP.
If the TSAUXC.ST0/1 flag is cleared, it happens instantly when setting the
TSAUXC.EN_CLK0/1 bit.
Otherwise it happens when the SYSTIM is >= the TRGTTIM.
Before the fix, when stopping PPS, only the SDP pin is disabled.
Therefore when starting PPS again, as soon as the SDP pin is enabled,
the clock output starts.
This fix will correctly clear the TSAUXC.ST0/1 and TSAUXC.EN_CLK0/1 bits
when stopping PPS. This will ensure that the clock output only happen
when the SYSTIM is >= the TRGTTIM.
Signed-off-by: Roland Hii roland.king.guan.hii@intel.com