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feat!: Brillig typed memory #5395

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merged 26 commits into from
Mar 26, 2024
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c28292a
wip: typed memory early test
sirasistant Mar 22, 2024
e7c7835
tests: fix some tests
sirasistant Mar 22, 2024
8932313
tests: fix moar tests
sirasistant Mar 22, 2024
02abd5a
test: fix moar tests
sirasistant Mar 22, 2024
bfe3776
chore: update serialization
sirasistant Mar 22, 2024
85b57e5
fix: debugger for typed memory
sirasistant Mar 25, 2024
2b72121
feat: remove redundant modulos
sirasistant Mar 25, 2024
f2c621e
refactor: use tryinto for memory values
sirasistant Mar 25, 2024
d3f3c7c
Merge branch 'master' into arv/brillig_typed_memory
sirasistant Mar 25, 2024
e47316e
chore: update inline snap
sirasistant Mar 25, 2024
5d5e596
fix: update deployer address
sirasistant Mar 25, 2024
98ecd29
chore: fix constant properly
sirasistant Mar 25, 2024
afb7d1a
fix: remove dup impl
sirasistant Mar 25, 2024
1bad484
fix: check constants to be within bit size
sirasistant Mar 25, 2024
078bb5d
fix: from u8
sirasistant Mar 25, 2024
f0f3199
refactor: extract write_foreign_call_result
sirasistant Mar 25, 2024
861bc8e
Merge branch 'master' into arv/brillig_typed_memory
sirasistant Mar 25, 2024
00ebf0b
chore: update artifact hash
sirasistant Mar 25, 2024
9ca31c0
chore: update constants
sirasistant Mar 25, 2024
8f05338
fix: implementation of new_checked
sirasistant Mar 25, 2024
8a24739
fix: restore portaled bbjs
sirasistant Mar 26, 2024
e7bb64e
Merge branch 'master' into arv/brillig_typed_memory
sirasistant Mar 26, 2024
69f8647
perf: do not check const in runtime
sirasistant Mar 26, 2024
f5c199e
Merge branch 'arv/brillig_typed_memory' of github.com:AztecProtocol/a…
sirasistant Mar 26, 2024
b369ce4
refactor: Address PR comments
sirasistant Mar 26, 2024
2e931cd
Merge branch 'master' into arv/brillig_typed_memory
sirasistant Mar 26, 2024
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1 change: 1 addition & 0 deletions avm-transpiler/Cargo.lock

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7 changes: 4 additions & 3 deletions avm-transpiler/src/transpile.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,9 @@ use acvm::acir::brillig::Opcode as BrilligOpcode;
use acvm::acir::circuit::brillig::Brillig;

use acvm::brillig_vm::brillig::{
BinaryFieldOp, BinaryIntOp, BlackBoxOp, HeapArray, MemoryAddress, Value, ValueOrArray,
BinaryFieldOp, BinaryIntOp, BlackBoxOp, HeapArray, MemoryAddress, ValueOrArray,
};
use acvm::FieldElement;

use crate::instructions::{
AvmInstruction, AvmOperand, AvmTypeTag, ALL_DIRECT, FIRST_OPERAND_INDIRECT,
Expand Down Expand Up @@ -798,7 +799,7 @@ fn handle_getter_instruction(
fn handle_const(
avm_instrs: &mut Vec<AvmInstruction>,
destination: &MemoryAddress,
value: &Value,
value: &FieldElement,
bit_size: &u32,
) {
let tag = tag_from_bit_size(*bit_size);
Expand All @@ -808,7 +809,7 @@ fn handle_const(
avm_instrs.push(generate_set_instruction(tag, dest, value.to_u128()));
} else {
// We can't fit a field in an instruction. This should've been handled in Brillig.
let field = value.to_field();
let field = value;
if !field.fits_in_u128() {
panic!("SET: Field value doesn't fit in 128 bits, that's not supported!");
}
Expand Down
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