RISCV-HARDWARE DESIGN PROGRAM (https://www.vlsisystemdesign.com/hdp_riscv/)
Product-Based RISC-V Skilling Program
1. Exploring RISC-V's history, architecture, and Verilog simulations.
2. Unlocking processor functionalities with hands-on exercises.
3. Delving into Verilog code analysis and advanced instructions.
4. Mastering I/Os with practical, real-world implementations.
5. Enhancing programming with C code and inline assembly.
6. Learning testbench strategies and functional simulation techniques.
This course gave participants a comprehensive grasp of creating RISC-V-based embedded projects, covering everything from application code to Netlist. As part of the course curriculum, I got to use the Chipcron tool offered by RISC-V startup https://chipcron-pvt-ltd.github.io/webpage/, to generate a customized RISC-V core. Furthermore, by simulating application code on the created core, I was able to have hands-on experience and improve my understanding of RISC-V architecture and design techniques.
The weekly course curriculum includes the following:
- Install Oracle Virtual VM Machine via VDI.
- Create a GitHub repository to share your work with others.
- Execute C code for hello world, counters, and matrix multiplication with Assembly differences.
- Focus on binary arithmetic.
- Create an adder with C and Verilog code, utilizing Iverilog and gtkwave. Run the same program on Godbolt to create assembly instructions.
- Create a 4-bit arithmetic logic unit (ALU) with C and Verilog code, utilizing Iverilog and GTKWAVE. Run the same program on Godbolt to create assembly instructions.
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RISC-V-based MYTH workshop:
i. Introduction to RISC-V ISA and GNU compiler toolchain.
ii. Introduction to ABI and basic verification flow.
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Measurement of CPU performance metrics.
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Basic RISC-V Microarchitecture Implementation.
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Verify all the previous C codes in Week 1 and Week 2 using RISC-V compiler and SPIKE ISA simulator.
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CPU performance calculation of the assembly codes with those C programs using the RISC-V Disassembler.
PROJECT: "Obstacle Awareness for Individuals with Disabilities"
- An overview of the project.
- Key Components for designing the project.
- An outline of the project using a block diagram.
- Basic C code compilation using GCC compiler and RISC-V compiler.
- Simulating the code using SPIKE ISA simulator.
- Assembly code generation for the basic C code.
- Inline assembly code for the Obstacle detector.
- Testing the code with SPIKE ISA Simulator and Assembly code generation using RISC-V objdump command.
- Updating the .json file and generating the RTL design using the Chipcron Tool.
- GPIO Configuration and Functional Simulation using UART.
- Simulating it with the help of Icarus Verilog simulator.
- Waveform generation using the GTKWAVE.
- Bypassing the UART.
- Gate-level synthesis using the open-source Yosys synthesizing tool.
- Gate-level Simulation using Skywater 130nm PDK.
- Waveform generation using the GTKWAVE.