by Viktoria Biliouri
Implementation of a serial communication system using the UART (Universal Asynchronus Receiver Transmitter) protocol, for FPGA SPARTAN 3 console, on ISE Design Suite (Verilog).
The following verilog files, compose the full process for the implementation of a communication system using the UART protocol.
The uart_system.v module is the top module and the Testbench.v the tesbench file.
The full process of the project is described analytically in Report.pdf