signals: be more explicit with pointers

BloomyControls · Mar 31, 2023 · e7dcc88 · e7dcc88
1 parent 1218403
commit e7dcc88
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Showing 3 changed files with 5 additions and 5 deletions.
diff --git a/examples/examplemodel1/src/model.c b/examples/examplemodel1/src/model.c
@@ -1,7 +1,7 @@
 /*
  * Auto-generated VeriStand model interface code for my_new_model.
  *
- * Generated Thu Sep 08 12:07:35 2022
+ * Generated Fri Mar 31 11:00:09 2023
  *
  * You almost certainly do NOT want to edit this file, as it may be overwritten
  * at any time!
@@ -116,7 +116,7 @@ double USER_GetValueByDataType(void* ptr, int32_t idx, int32_t type) {
 
 int32_t USER_Initialize(void) {
   /* Populate pointers to signal values */
-  rtSignalAttribs[0].addr = (uintptr_t)rtSignal.i32_vec_sig;
+  rtSignalAttribs[0].addr = (uintptr_t)&*rtSignal.i32_vec_sig;
   rtSignalAttribs[1].addr = (uintptr_t)&rtSignal.double_sig;
 
   return my_new_model_Initialize();

diff --git a/examples/examplemodel1/src/model.h b/examples/examplemodel1/src/model.h
@@ -1,7 +1,7 @@
 /*
  * Auto-generated VeriStand model types for my_new_model.
  *
- * Generated Thu Sep 08 12:07:35 2022
+ * Generated Fri Mar 31 11:00:09 2023
  *
  * You almost certainly do NOT want to edit this file, as it may be overwritten
  * at any time!

diff --git a/genvsmodel.py b/genvsmodel.py
@@ -714,9 +714,9 @@ def FmtSignalInit(signals) -> str:
             if sig["dimX"] == 1 and sig["dimY"] == 1:
                 prefix = '&'
             elif sig["dimX"] > 1 and sig["dimY"] == 1:
-                prefix = ''
+                prefix = '&*'
             elif sig["dimX"] > 1 and sig["dimY"] > 1:
-                prefix = '*'
+                prefix = '&**'
             catname = '' if cat == ':default' else '.' + cat
             outstr += f'{prefix}rtSignal{catname}.{sig["name"]};\n'
             i += 1