Functional Design

AISO.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//	Author: 		Brandon Torres
+//	Email:  		Brandon0torres@gmail.com
+//	Filename:	AISO.v
+//	
+//	Notes:		The module has two flip flops that are connected to the same clock 
+//					as the rest of the modules. This module will take an asynchronous 
+//					signal in and then output a synchronous signal.
+//////////////////////////////////////////////////////////////////////////////////
+module AISO(clk,async_in,sync_out);
+	input clk,async_in;
+	output wire sync_out;
+	reg inreg,outreg;
+
+	always @(posedge clk, posedge async_in)begin
+		if(async_in)
+			inreg<=0;
+		else
+			inreg<=1;
+
+	end
+
+	always @(posedge clk)
+		outreg<=inreg;
+
+	assign sync_out=outreg;		
+
+
+endmodule

Baud_Counter.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//	Author: 		Brandon Torres
+//	Email:  		Brandon0torres@gmail.com
+//	Filename:	Baud_Counter.v
+//	
+//	Notes:		The Baud rate is only set on reset and cannot be changed during run.
+//					The module sets the Baud rate for the UART depending on the user 
+//					input. Once the Baud time has passed then BTU is set for one clock.
+//////////////////////////////////////////////////////////////////////////////////
+module Baud_Counter(clk,reset,Start,Baud_Val,BTU);
+	 input clk,reset,Start;
+	 input [3:0] Baud_Val;
+	 output wire BTU;
+
+	 reg [17:0] count_val;
+	 reg [17:0] q_reg;
+	 wire[17:0] q_next;
+
+	 always @(posedge clk, negedge reset)
+		if(!reset)begin
+			q_reg<=0;
+			 case(Baud_Val)
+				4'b0000: count_val<=166666; //300 Baud
+				4'b0001: count_val<=83332;  //600 Baud
+				4'b0010: count_val<=41666;  //1200 Baud
+				4'b0011: count_val<=20832;  //2400 Baud
+				4'b0100: count_val<=10416;  //4800 Baud
+				4'b0101: count_val<=5207;   //9600 Baud
+				4'b0110: count_val<=2603;   //19200 Baud
+				4'b0111: count_val<=1760;   //28400 Baud
+				4'b1000: count_val<=867;    //57600 Baud
+				4'b1001: count_val<=433;    //115200 Baud
+				4'b1010: count_val<=216;    //230400 Baud
+				4'b1011: count_val<=108;    //460800 Baud
+				4'b1100: count_val<=53;     //921600 Baud
+				default: count_val<=166666; //Default is 300 Baud
+			endcase
+		end
+		else if(BTU)
+			q_reg<=0;
+		else if(Start)
+			q_reg<=q_next;
+		else
+			q_reg<=0;
+
+	assign q_next=q_reg+1;
+
+	//set tick when after each BTU 
+	assign BTU= (q_reg==count_val) ? 1'b1 : 1'b0;
+
+
+endmodule

Baud_Decoder.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//	Author: 		Brandon Torres
+//	Email:  		Brandon0torres@gmail.com
+//	Filename:	Baud_Decoder.v
+//	
+//	Notes:		The module interconnects Baud_Counter and Bit_Counter. Bit_Counter 
+//					counts every BTU and sets Done once 11 BTU have occurred.
+//////////////////////////////////////////////////////////////////////////////////
+module Baud_Decoder(clk,reset,Start,Done,Baud_Val,BTU);
+	input clk,reset,Start;
+	input[3:0] Baud_Val;
+	output wire Done,BTU;
+
+	Baud_Counter bc(.clk(clk),.reset(reset),.Start(Start),.Baud_Val(Baud_Val),
+						 .BTU(BTU));
+
+	Bit_Counter bitc(.clk(clk),.reset(reset),.BTU(BTU),.Done(Done));
+
+
+endmodule

Baud_Delay.v

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+//////////////////////////////////////////////////////////////////////////////////
+//	Author: 		Brandon Torres
+//	Email:  		Brandon0torres@gmail.com
+//	Filename:	Baud_Counter.v
+//	
+//	Notes:		The Baud rate is only set on reset and cannot be changed during run.
+//					The module sets the Baud rate for the UART depending on the user 
+//					input. Once the Baud time has passed then BTU is set for one clock.
+//////////////////////////////////////////////////////////////////////////////////
+module Baud_Delay(clk,reset,Start,Baud_Val,BTU);
+	 input clk,reset,Start;
+	 input [3:0] Baud_Val;
+	 output wire BTU;
+
+	 reg [17:0] count_val;
+	 reg [17:0] q_reg;
+	 wire[17:0] q_next;
+
+	 always @(posedge clk, negedge reset)
+		if(!reset)begin
+			q_reg<=0;
+			 case(Baud_Val)
+				4'b0000: count_val<=166666/2; //300 Baud
+				4'b0001: count_val<=83332/2;  //600 Baud
+				4'b0010: count_val<=41666/2;  //1200 Baud
+				4'b0011: count_val<=20832/2;  //2400 Baud
+				4'b0100: count_val<=10416/2;  //4800 Baud
+				4'b0101: count_val<=5207/2;   //9600 Baud
+				4'b0110: count_val<=2603/2;   //19200 Baud
+				4'b0111: count_val<=1760/2;   //28400 Baud
+				4'b1000: count_val<=867/2;    //57600 Baud
+				4'b1001: count_val<=433/2;    //115200 Baud
+				4'b1010: count_val<=216/2;    //230400 Baud
+				4'b1011: count_val<=108/2;    //460800 Baud
+				4'b1100: count_val<=53/2;     //921600 Baud
+				default: count_val<=166666/2; //Default is 300 Baud
+			endcase
+		end
+		else if(!Start)
+			q_reg<=0;
+		else if(BTU)
+			q_reg<=q_reg;
+		else
+			q_reg<=q_next;
+
+	assign q_next=q_reg+1;
+	//set tick when after each BTU 
+	assign BTU= (q_reg==count_val) ? 1'b1 : 1'b0;
+
+
+endmodule

Bit_Counter.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//	Author: 		Brandon Torres
+//	Email:  		Brandon0torres@gmail.com
+//	Filename:	Bit_Counter.v
+//	
+//	Notes:		The module is a simple counter that increments every time it
+//					receives BTU. Once eleven BTU have occurred then the Done signal is
+//					set.
+//////////////////////////////////////////////////////////////////////////////////
+module Bit_Counter(clk,reset,BTU,Done);
+	input clk,reset,BTU;
+	output wire Done;
+	reg [3:0] q_reg;
+
+	always @(posedge clk, negedge reset)
+		if(!reset)
+			q_reg<=4'b0;
+		else if(BTU)
+			q_reg<=q_reg+1;
+		else if(q_reg==11)
+			q_reg<=4'b0;
+		else
+			q_reg<=q_reg;
+	assign Done=(q_reg==11) ? 1'b1 : 1'b0;	
+
+endmodule