fix: allow dominator edges in CFGBuilder

CQCL · Nov 7, 2023 · 936ebeb · 936ebeb
1 parent 24a6144
commit 936ebeb
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Showing 2 changed files with 40 additions and 5 deletions.
diff --git a/src/builder/build_traits.rs b/src/builder/build_traits.rs
@@ -2,7 +2,7 @@ use crate::hugr::hugrmut::InsertionResult;
 use crate::hugr::validate::InterGraphEdgeError;
 use crate::hugr::views::HugrView;
 use crate::hugr::{NodeMetadata, ValidationError};
-use crate::ops::{self, LeafOp, OpTrait, OpType};
+use crate::ops::{self, LeafOp, OpTag, OpTrait, OpType};
 use crate::{IncomingPort, Node, OutgoingPort};
 
 use std::iter;
@@ -668,6 +668,7 @@ fn wire_up<T: Dataflow + ?Sized>(
     let base = data_builder.hugr_mut();
 
     let src_parent = base.get_parent(src);
+    let src_parent_parent = src_parent.and_then(|src| base.get_parent(src));
     let dst_parent = base.get_parent(dst);
     let local_source = src_parent == dst_parent;
     if let EdgeKind::Value(typ) = base.get_optype(src).port_kind(src_port).unwrap() {
@@ -689,7 +690,10 @@ fn wire_up<T: Dataflow + ?Sized>(
             let Some(src_sibling) = iter::successors(dst_parent, |&p| base.get_parent(p))
                 .tuple_windows()
                 .find_map(|(ancestor, ancestor_parent)| {
-                    (ancestor_parent == src_parent).then_some(ancestor)
+                    (ancestor_parent == src_parent ||
+                        // Dom edge - in CFGs
+                        Some(ancestor_parent) == src_parent_parent)
+                        .then_some(ancestor)
                 })
             else {
                 let val_err: ValidationError = InterGraphEdgeError::NoRelation {
@@ -702,9 +706,12 @@ fn wire_up<T: Dataflow + ?Sized>(
                 return Err(val_err.into());
             };
 
-            // TODO: Avoid adding duplicate edges
-            // This should be easy with https://github.com/CQCL-DEV/hugr/issues/130
-            base.add_other_edge(src, src_sibling)?;
+            if !OpTag::BasicBlock.is_superset(base.get_optype(src).tag())
+                && !OpTag::BasicBlock.is_superset(base.get_optype(src_sibling).tag())
+            {
+                // Add a state order constraint unless one of the nodes is a CFG BasicBlock
+                base.add_other_edge(src, src_sibling)?;
+            }
         } else if !typ.copyable() & base.linked_ports(src, src_port).next().is_some() {
             // Don't copy linear edges.
             return Err(BuildError::NoCopyLinear(typ));

diff --git a/src/builder/cfg.rs b/src/builder/cfg.rs
@@ -393,4 +393,32 @@ mod test {
         cfg_builder.branch(&entry, 1, &exit)?;
         Ok(())
     }
+    #[test]
+    fn test_dom_edge() -> Result<(), BuildError> {
+        let mut cfg_builder = CFGBuilder::new(FunctionType::new(type_row![NAT], type_row![NAT]))?;
+        let sum_tuple_const =
+            cfg_builder.add_constant(ops::Const::unary_unit_sum(), ExtensionSet::new())?;
+        let sum_variants = vec![type_row![]];
+
+        let mut entry_b =
+            cfg_builder.entry_builder(sum_variants.clone(), type_row![], ExtensionSet::new())?;
+        let [inw] = entry_b.input_wires_arr();
+        let entry = {
+            let sum = entry_b.load_const(&sum_tuple_const)?;
+
+            entry_b.finish_with_outputs(sum, [])?
+        };
+        let exit = cfg_builder.exit_block();
+        let mut middle_b =
+            cfg_builder.simple_block_builder(FunctionType::new(type_row![], type_row![NAT]), 1)?;
+        let middle = {
+            let c = middle_b.load_const(&sum_tuple_const)?;
+            middle_b.finish_with_outputs(c, [inw])?
+        };
+        cfg_builder.branch(&entry, 0, &middle)?;
+        cfg_builder.branch(&middle, 0, &exit)?;
+        assert_matches!(cfg_builder.finish_prelude_hugr(), Ok(_));
+
+        Ok(())
+    }
 }