Merge pull request #80 from CQCL/release/0.3.0

Release/0.3.0

.github/workflows/build_and_test.yml

@@ -26,7 +26,7 @@ jobs:
         os: ['ubuntu-22.04', 'macos-12', 'windows-2022']
     runs-on: ${{ matrix.os }}
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
       with:
         fetch-depth: '0'
     - run: git fetch --depth=1 origin +refs/tags/*:refs/tags/* +refs/heads/*:refs/remotes/origin/*
@@ -111,7 +111,7 @@ jobs:
     needs: publish_to_pypi
     runs-on: ubuntu-22.04
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
       with:
         fetch-depth: '0'
     - name: Set up Python 3.10

.github/workflows/docs.yml

@@ -12,7 +12,7 @@ jobs:
     name: build docs
     runs-on: ubuntu-22.04
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
     - name: Set up Python 3.10
       uses: actions/setup-python@v4
       with:

.github/workflows/lint.yml

@@ -18,7 +18,7 @@ jobs:
     runs-on: ubuntu-22.04
 
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
     - name: Set up Python 3.x
       uses: actions/setup-python@v4
       with:

_metadata.py

@@ -1,2 +1,2 @@
-__extension_version__ = "0.2.0"
+__extension_version__ = "0.3.0"
 __extension_name__ = "pytket-qir"

docs/changelog.rst

@@ -1,6 +1,10 @@
 Changelog
 ~~~~~~~~~
 
+0.3.0 (September 2023)
+----------------------
+* update pytket version to 1.20
+
 0.2.0 (August 2023)
 -------------------
 * fix issue with integer in regular expression

mypy.ini

@@ -14,7 +14,7 @@ namespace_packages = True
 check_untyped_defs = True
 
 warn_redundant_casts = True
-warn_unused_ignores = False
+warn_unused_ignores = True
 warn_no_return = False
 warn_return_any = True
 warn_unreachable = True

pytket/qir/__init__.py

@@ -16,5 +16,5 @@
 """
 
 # _metadata.py is copied to the folder after installation.
-from ._metadata import __extension_name__, __extension_version__  # type: ignore
+from ._metadata import __extension_name__, __extension_version__
 from .conversion import QIRFormat, pytket_to_qir

pytket/qir/conversion/api.py

@@ -22,9 +22,9 @@
 import pyqir
 
 from pytket import wasm
-from pytket._tket.circuit import _TEMP_BIT_NAME  # type: ignore
-from pytket.circuit import Bit, Circuit  # type: ignore
-from pytket.passes import CustomPass  # type: ignore
+from pytket.circuit import Bit, Circuit, UnitID
+from pytket.passes import CustomPass
+from pytket.unit_id import _TEMP_BIT_NAME
 
 from .conversion import QirGenerator
 from .module import tketqirModule
@@ -73,7 +73,7 @@ def pytket_to_qir(
 
     if cut_pytket_register:
         cpass = _scratch_reg_resize_pass(int_type)
-        cpass.apply(circ)
+        cpass.apply(circ)  # type: ignore
 
     for creg in circ.c_registers:
         if creg.size > 64:
@@ -96,19 +96,19 @@ def pytket_to_qir(
     if wfh is not None:
         wasm_sar_dict: dict[str, str] = qir_generator.get_wasm_sar()
 
-        initial_result = str(populated_module.module.ir())  # type: ignore
+        initial_result = str(populated_module.module.ir())
 
         for wf in wasm_sar_dict:
             initial_result = initial_result.replace(wf, wasm_sar_dict[wf])
 
         result = initial_result
 
-        bitcode = pyqir.Module.from_ir(pyqir.Context(), result).bitcode  # type: ignore
+        bitcode = pyqir.Module.from_ir(pyqir.Context(), result).bitcode
 
         if qir_format == QIRFormat.BINARY:
-            return bitcode  # type: ignore
+            return bitcode
         elif qir_format == QIRFormat.STRING:
-            return result  # type: ignore
+            return result
         else:
             assert not "unsupported return type"  # type: ignore
 
@@ -121,7 +121,7 @@ def pytket_to_qir(
             assert not "unsupported return type"  # type: ignore
 
 
-def _scratch_reg_resize_pass(max_size: int) -> CustomPass:
+def _scratch_reg_resize_pass(max_size: int) -> CustomPass:  # type: ignore
     """Given a max scratch register width, return a compiler pass that
     breaks up the internal scratch bit registers into smaller registers
     """
@@ -138,7 +138,7 @@ def trans(circ: Circuit, max_size: int = max_size) -> Circuit:
         ]
         # If the total number of scratch bits exceeds the max width, rename them
         if len(scratch_bits) > max_size:
-            bits_map = {}
+            bits_map: dict[UnitID, UnitID] = {}
             for i, bit in enumerate(scratch_bits):
                 bits_map[bit] = Bit(f"{_TEMP_BIT_NAME}_{i//max_size}", i % max_size)
             circ.rename_units(bits_map)

pytket/qir/conversion/conversion.py

@@ -26,20 +26,20 @@
 from pyqir import IntPredicate, Value
 
 from pytket import Bit, Circuit, Qubit, predicates, wasm  # type: ignore
-from pytket.circuit import (  # type: ignore
+from pytket.circuit import (
+    BarrierOp,
     BitRegister,
     ClassicalExpBox,
     Command,
     Conditional,
     CopyBitsOp,
-    MetaOp,
     Op,
     OpType,
     RangePredicateOp,
     SetBitsOp,
     WASMOp,
 )
-from pytket.circuit.logic_exp import (  # type: ignore
+from pytket.circuit.logic_exp import (
     BitAnd,
     BitEq,
     BitNeq,
@@ -61,8 +61,8 @@
     RegSub,
     RegXor,
 )
-from pytket.qasm.qasm import _retrieve_registers  # type: ignore
-from pytket.transform import Transform  # type: ignore
+from pytket.qasm.qasm import _retrieve_registers
+from pytket.transform import Transform
 
 from .gatesets import (
     FuncSpec,
@@ -132,7 +132,9 @@ def __init__(
         self.target_gateset.add(OpType.ZZMax)
         self.target_gateset.add(OpType.TK2)
 
-        self.getset_predicate = predicates.GateSetPredicate(set(self.target_gateset))  # type: ignore  # noqa: E501
+        self.getset_predicate = predicates.GateSetPredicate(
+            set(self.target_gateset)
+        )  # noqa: E501
 
         self.set_cregs: dict[str, list] = {}  # Keep track of set registers.
         self.ssa_vars: dict[str, Value] = {}  # Keep track of set ssa variables.
@@ -388,7 +390,7 @@ def _rebase_command_to_gateset(self, command: Command) -> Optional[Circuit]:
             return circuit
         return None
 
-    def _rebase_op_to_gateset(self, op: OpType, args: list) -> Optional[Circuit]:
+    def _rebase_op_to_gateset(self, op: Op, args: list) -> Optional[Circuit]:
         """Rebase an op to the target gateset if needed."""
         optype = op.type
         if (
@@ -420,16 +422,9 @@ def _rebase_op_to_gateset(self, op: OpType, args: list) -> Optional[Circuit]:
             return circuit
 
     def _get_optype_and_params(self, op: Op) -> tuple[OpType, Sequence[float]]:
-        optype = op.type
+        optype: OpType = op.type
         params: list = []
-        if optype == OpType.ExplicitPredicate:
-            if op.get_name() == "AND":
-                optype = BitWiseOp.AND
-            elif op.get_name() == "OR":
-                optype = BitWiseOp.OR
-            elif op.get_name() == "XOR":
-                optype = BitWiseOp.XOR
-        elif optype in [OpType.Barrier, OpType.CopyBits]:
+        if optype in [OpType.ExplicitPredicate, OpType.Barrier, OpType.CopyBits]:
             pass
         else:
             params = op.params
@@ -465,7 +460,7 @@ def _reg2ssa_var(self, bit_reg: BitRegister, int_size: int) -> Value:
                 raise ValueError(
                     f"Classical register should only have the size of {int_size}"
                 )
-            ssa_var = self.module.builder.call(  # type: ignore
+            ssa_var = self.module.builder.call(
                 self.create_creg, [pyqir.const(self.qir_int_type, len(bit_reg))]
             )
             self.ssa_vars[reg_name] = ssa_var
@@ -490,7 +485,7 @@ def _get_c_regs_from_com(self, command: Command) -> tuple[list[str], list[str]]:
                     com_bits = args[:in_width]
                     args = args[in_width:]
                     regname = com_bits[0].reg_name
-                    if com_bits != list(self.cregs[regname]):
+                    if com_bits != list(self.cregs[regname]):  # type: ignore
                         raise ValueError("WASM ops must act on entire registers.")
                     reglist.append(regname)
         return inputs, outputs
@@ -499,10 +494,12 @@ def _get_ssa_from_cl_reg_op(
         self, reg: Union[BitRegister, RegAnd, RegOr, RegXor], module: tketqirModule
     ) -> Value:
         if type(reg) in _TK_CLOPS_TO_PYQIR_REG:
-            assert len(reg.args) == 2
+            assert len(reg.args) == 2  # type: ignore
 
-            ssa_left = self._get_ssa_from_cl_reg_op(reg.args[0], module)
-            ssa_right = self._get_ssa_from_cl_reg_op(reg.args[1], module)
+            ssa_left = self._get_ssa_from_cl_reg_op(reg.args[0], module)  # type: ignore
+            ssa_right = self._get_ssa_from_cl_reg_op(
+                reg.args[1], module  # type: ignore
+            )
 
             # add function to module
             output_instruction = _TK_CLOPS_TO_PYQIR_REG[type(reg)](module.builder)(
@@ -648,8 +645,8 @@ def condition_block_false() -> None:
 
                     module.module.builder.if_(
                         ssabool,
-                        true=lambda: condition_block_true(),  # type: ignore
-                        false=lambda: condition_block_false(),  # type: ignore
+                        true=lambda: condition_block_true(),
+                        false=lambda: condition_block_false(),
                     )
 
                 else:
@@ -685,15 +682,15 @@ def condition_block() -> None:
 
                     module.module.builder.if_(
                         ssabool,
-                        true=lambda: condition_block(),  # type: ignore
+                        true=lambda: condition_block(),
                     )
 
             elif isinstance(op, WASMOp):
                 paramreg, resultreg = self._get_c_regs_from_com(command)
 
                 paramssa = [self._get_i64_ssa_reg(p) for p in paramreg]
 
-                result = self.module.builder.call(  # type: ignore
+                result = self.module.builder.call(
                     self.wasm[command.op.func_name],
                     [*paramssa],
                 )
@@ -724,7 +721,7 @@ def condition_block() -> None:
                         ),
                     )
 
-                self.module.builder.call(  # type: ignore
+                self.module.builder.call(
                     self.additional_quantum_gates[OpType.ZZPhase],
                     [
                         pyqir.const(
@@ -756,7 +753,7 @@ def condition_block() -> None:
                         ),
                     )
 
-                self.module.builder.call(  # type: ignore
+                self.module.builder.call(
                     self.additional_quantum_gates[OpType.PhasedX],
                     [
                         pyqir.const(
@@ -793,7 +790,7 @@ def condition_block() -> None:
                         ),
                     )
 
-                self.module.builder.call(  # type: ignore
+                self.module.builder.call(
                     self.additional_quantum_gates[OpType.TK2],
                     [
                         pyqir.const(
@@ -832,7 +829,7 @@ def condition_block() -> None:
                         ),
                     )
 
-                self.module.builder.call(  # type: ignore
+                self.module.builder.call(
                     self.additional_quantum_gates[OpType.ZZMax],
                     [
                         module.module.qubits[command.qubits[0].index[0]],
@@ -883,11 +880,15 @@ def condition_block() -> None:
                     # classical ops acting on registers returning register
                     ssa_left = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_reg_op(op.get_exp().args[0], module),
+                        self._get_ssa_from_cl_reg_op(
+                            op.get_exp().args[0], module  # type: ignore
+                        ),
                     )
                     ssa_right = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_reg_op(op.get_exp().args[1], module),
+                        self._get_ssa_from_cl_reg_op(
+                            op.get_exp().args[1], module  # type: ignore
+                        ),
                     )
 
                     # add function to module
@@ -899,11 +900,15 @@ def condition_block() -> None:
                     # classical ops acting on bits returning bit
                     ssa_left = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_bit_op(op.get_exp().args[0], module),
+                        self._get_ssa_from_cl_bit_op(
+                            op.get_exp().args[0], module  # type: ignore
+                        ),
                     )
                     ssa_right = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_bit_op(op.get_exp().args[1], module),
+                        self._get_ssa_from_cl_bit_op(
+                            op.get_exp().args[1], module  # type: ignore
+                        ),
                     )
 
                     # add function to module
@@ -917,11 +922,15 @@ def condition_block() -> None:
                     # classical ops acting on registers returning bit
                     ssa_left = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_reg_op(op.get_exp().args[0], module),
+                        self._get_ssa_from_cl_reg_op(
+                            op.get_exp().args[0], module  # type: ignore
+                        ),
                     )
                     ssa_right = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_reg_op(op.get_exp().args[1], module),
+                        self._get_ssa_from_cl_reg_op(
+                            op.get_exp().args[1], module  # type: ignore
+                        ),
                     )
 
                     # add function to module
@@ -993,7 +1002,7 @@ def condition_block() -> None:
                         ],
                     )
 
-            elif isinstance(op, MetaOp):
+            elif isinstance(op, BarrierOp):
                 assert command.qubits[0].reg_name == "q"
 
                 qir_qubits = self._to_qis_qubits(command.qubits)
@@ -1012,7 +1021,7 @@ def condition_block() -> None:
                         float(command.op.data[6:-1]),
                     )
                 else:
-                    raise ValueError("Meta op is not supported yet")
+                    raise ValueError("op is not supported yet")
 
             else:
                 rebased_circ = self._rebase_command_to_gateset(

pytket/qir/conversion/module.py

@@ -19,7 +19,7 @@
 
 from typing import Optional
 
-from pyqir import BasicQisBuilder, SimpleModule  # type: ignore
+from pyqir import BasicQisBuilder, SimpleModule
 
 from pytket.wasm import WasmFileHandler
 

setup.py

@@ -45,7 +45,7 @@
     packages=find_namespace_packages(include=["pytket.*"]),
     include_package_data=True,
     install_requires=[
-        "pytket == 1.19.0rc0",
+        "pytket ~= 1.20",
         "pyqir == 0.8.2",
         "pyqir-generator == 0.7.0",
         "pyqir-evaluator == 0.7.0",