mypy fix (#82)

* fix error message * fix mypy * format * add int as type to func
CQCL · Oct 17, 2023 · f1f3206 · f1f3206
1 parent 55cf60d
commit f1f3206
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Showing 2 changed files with 10 additions and 14 deletions.
diff --git a/pytket/qir/conversion/conversion.py b/pytket/qir/conversion/conversion.py
@@ -485,13 +485,13 @@ def _get_c_regs_from_com(self, command: Command) -> tuple[list[str], list[str]]:
                     com_bits = args[:in_width]
                     args = args[in_width:]
                     regname = com_bits[0].reg_name
-                    if com_bits != list(self.cregs[regname]):  # type: ignore
+                    if com_bits != list(self.cregs[regname]):
                         raise ValueError("WASM ops must act on entire registers.")
                     reglist.append(regname)
         return inputs, outputs
 
     def _get_ssa_from_cl_reg_op(
-        self, reg: Union[BitRegister, RegAnd, RegOr, RegXor], module: tketqirModule
+        self, reg: Union[BitRegister, RegAnd, RegOr, RegXor, int], module: tketqirModule
     ) -> Value:
         if type(reg) in _TK_CLOPS_TO_PYQIR_REG:
             assert len(reg.args) == 2  # type: ignore
@@ -900,15 +900,11 @@ def condition_block() -> None:
                     # classical ops acting on bits returning bit
                     ssa_left = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_bit_op(
-                            op.get_exp().args[0], module  # type: ignore
-                        ),
+                        self._get_ssa_from_cl_bit_op(op.get_exp().args[0], module),
                     )
                     ssa_right = cast(  # type: ignore
                         Value,
-                        self._get_ssa_from_cl_bit_op(
-                            op.get_exp().args[1], module  # type: ignore
-                        ),
+                        self._get_ssa_from_cl_bit_op(op.get_exp().args[1], module),
                     )
 
                     # add function to module
@@ -940,7 +936,7 @@ def condition_block() -> None:
                     ](module.builder)(ssa_left, ssa_right)
 
                 else:
-                    raise ValueError(" unexpected classical op")
+                    raise ValueError(f"unexpected classical op {type(op.get_exp())}")
 
                 if returntypebool:
                     # the return value of the some classical ops is bool in qir,

diff --git a/tests/conversion_test.py b/tests/conversion_test.py
@@ -157,7 +157,7 @@ def test_pytket_qir_8() -> None:
     c.add_c_setbits([True], [a[2]])
     c.add_c_setbits([True], [a[1]])
     c.add_c_setbits([True], [a[7]])
-    c.add_c_setbits([False, True] + [False] * 6, list(a))  # type: ignore
+    c.add_c_setbits([False, True] + [False] * 6, list(a))
 
     result = pytket_to_qir(c, name="test_pytket_qir_8", qir_format=QIRFormat.STRING)
 
@@ -237,8 +237,8 @@ def test_pytket_qir_14() -> None:
     d = c.add_c_register("d", 10)
 
     c.add_c_setbits([True], [a[0]])
-    c.add_c_setbits([False, True] + [False] * 6, list(a))  # type: ignore
-    c.add_c_setbits([True, True] + [False] * 8, list(b))  # type: ignore
+    c.add_c_setbits([False, True] + [False] * 6, list(a))
+    c.add_c_setbits([True, True] + [False] * 8, list(b))
 
     c.add_c_setreg(23, a)
     c.add_c_copyreg(a, b)
@@ -276,8 +276,8 @@ def test_pytket_qir_14_b() -> None:
     d = c.add_c_register("d", 32)
 
     c.add_c_setbits([True], [a[0]])
-    c.add_c_setbits([False, True] + [False] * 30, list(a))  # type: ignore
-    c.add_c_setbits([True, True] + [False] * 30, list(b))  # type: ignore
+    c.add_c_setbits([False, True] + [False] * 30, list(a))
+    c.add_c_setbits([True, True] + [False] * 30, list(b))
 
     c.add_c_setreg(23, a)
     c.add_c_copyreg(a, b)