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Releases: CSpyridakis/Tomasulo
Releases · CSpyridakis/Tomasulo
Milestone-3
-Milestone-3:
- Reorder Buffer implementation
- Timing Diagram created
Milestone-2
-Milestone-2:
* Tomasulo (Top Module implementation)
* RS testbench and simulation updated (I-type)
* ISSUE testbench and simulation updated
* RF testbench and simulation updated
Milestone-1b
-Milestone-1b:
* ISSUE unit implemented
* RS unit implemented
* FU unit implemented
* CDB unit implemented
* RF unit implemented
Milestone-1
Milestone-1a:
* I/O connections specified for each unit
* Diagrams for each individual unit
* Top Diagram
* Report explaining above