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Log changes to most Arm32 registers #253

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Jul 2, 2024
Merged

Log changes to most Arm32 registers #253

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14 changes: 12 additions & 2 deletions target/arm/cpu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -244,6 +244,11 @@ typedef uint64_t AARCH_REG_TYPE;
#define N_BANK_WITH_RESTRICTED 4
#endif

extern const char * const arm32_regnames[16];
#ifdef TARGET_AARCH64
extern const char * const arm64_regnames[32];
#endif

typedef struct CPUARMState {
/* Regs for current mode. */
uint32_t regs[16];
Expand Down Expand Up @@ -3574,6 +3579,7 @@ typedef CPUARMState CPUArchState;
typedef ARMCPU ArchCPU;

#include "exec/cpu-all.h"
#include "exec/log_instr.h"
#include "cpu_cheri.h"
#include "cheri-lazy-capregs.h"

Expand All @@ -3594,11 +3600,15 @@ static inline void arm_set_xreg(CPUARMState *env, int regnum,
#ifdef TARGET_CHERI
update_capreg_to_intval(env, regnum, value);
#else
#ifdef TARGET_AARCH64
if (is_a64(env)) {
env->xregs[regnum] = value;
} else {
env->regs[regnum] = value;
qemu_log_instr_reg(env, arm64_regnames[regnum], value);
return;
}
#endif
env->regs[regnum] = value;
qemu_log_instr_reg(env, arm32_regnames[regnum], value);
#endif
}

Expand Down
1 change: 1 addition & 0 deletions target/arm/op_helper.c
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Expand Up @@ -453,6 +453,7 @@ void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
env->usr_regs[regno - 8] = val;
} else {
env->regs[regno] = val;
qemu_log_instr_reg(env, arm32_regnames[regno], val);
}
}

Expand Down
6 changes: 3 additions & 3 deletions target/arm/translate-a64.c
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Expand Up @@ -123,7 +123,7 @@ static inline bool get_sctlr_sa(DisasContext *ctx)
/* Load/store exclusive handling */
static TCGv_i64 cpu_exclusive_high;

static const char *regnames[] = {
const char * const arm64_regnames[32] = {
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
Expand Down Expand Up @@ -169,11 +169,11 @@ void a64_translate_init(void)
_cpu_cursors_do_not_access_directly[i] = tcg_global_mem_new(
cpu_env,
offsetof(CPUARMState, gpcapregs.decompressed[i].cap._cr_cursor),
regnames[i]);
arm64_regnames[i]);
#else
cpu_X[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUARMState, xregs[i]),
regnames[i]);
arm64_regnames[i]);
#endif
}

Expand Down
14 changes: 12 additions & 2 deletions target/arm/translate.c
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Expand Up @@ -98,7 +98,7 @@ TCGv_i64 cpu_exclusive_val;

#include "exec/gen-icount.h"

static const char * const regnames[] =
const char * const arm32_regnames[16] =
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };

Expand All @@ -116,7 +116,7 @@ void arm_translate_init(void)
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUARMState, regs[i]),
regnames[i]);
arm32_regnames[i]);
}
cpu_CF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), "CF");
cpu_NF = tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), "NF");
Expand Down Expand Up @@ -315,6 +315,16 @@ static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
s->base.is_jmp = DISAS_JUMP;
}
tcg_gen_mov_i32(cpu_R[reg], var);
#ifdef CONFIG_TCG_LOG_INSTR
if (qemu_ctx_logging_enabled(s)) {
TCGv_ptr name = tcg_const_ptr(arm32_regnames[reg]);
TCGv new_val = tcg_temp_new();
tcg_gen_extu_i32_tl(new_val, var);
gen_helper_qemu_log_instr_reg(cpu_env, name, new_val);
tcg_temp_free(new_val);
tcg_temp_free_ptr(name);
}
#endif
tcg_temp_free_i32(var);
}

Expand Down
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